The ChipList, by Adrian Offerman; The Processor Portal

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7  Intel Pentium P5 processors, AMD 5x86/6x86 processors

7.1  Intel Pentium processor

Generation


Generation: P5.

Compatibility


2-issue 5-stage superscalar with 8-stage pipelined FPU (Floating Point Unit).
Intel i80486 CPU upward instruction compatible.

System Management Mode (SMM).

Cache


8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture).
Both 2-way set-associative, write-back, no write-allocate.

Architecture


Branch prediction (BTB: Branch Target Buffer).

32 bit internal data bus (CPU - MMU (Memory Management Unit, including cache))
64 bit external data bus (MMU, including cache - memory).
Separate address space for instructions and data (Harvard architecture).

Parity checking at busses.

Multi-processing


Multi-processor support.
Upgrading: adding another Intel Pentium CPU.

Marking


  • processor type, clock speed:
    • A80502133: 133 MHz Pentium,
  • stepping and quality:
    • SY022/SSS:
      • SY022: lithography mask number:
        • s-spec (part characteristics): SK, SU, SX, SY, SZ,
      • S: Standard voltage (3.135 - 3.6 V), V (VRE): narrowed voltages 3.4 - 3.6 V,
      • S: Standard timing, M: Minimum Valid MD timing,
      • S: Standard configuration, U: Uniprocessor only,
  • embossed iPP mark: carried by all Pentium CPUs at 90 MHz and faster, most 75 MHz Pentium CPUs carry only the i75 mark, 90 MHz and faster Pentium CPUs with the i75 mark are most likely fake,
  • iCOMP index,
  • serial number:
    • 6044482-0591: number and serial number,
  • country of manufacture:
    • MALAY: Malayasia.

Bug


FDIV bug: In October 1994, Dr. Thomas R. Nicely, then Professor of Mathematics at the Lynchburg College, Lynchburg, Virginia, reported a bug present in the FPU of all Intel Pentium CPUs. The double precision part of the mantissa is not computed correctly when dividing in some areas of the mantissa space of the divisor. The bug is fixed in Intel Pentium CPUs produced after November 1994.


7.1.1  Intel Pentium P5 processor

7.1.2  Intel Pentium P54C processor

7.2  Intel Overdrive processor for Intel Pentium processor

Compatibility


System Management Mode (SMM).


7.2.1  Intel Pentium P54M processor

7.2.2  Intel Pentium OverDrive processor

7.3  AMD K5 processor

Identification


Model name: K5.
Family name: K86 series.
Supplier: AMD.
Component class: CPU.

Generation


Generation: K5.

Compatibility


Intel Pentium CPU compatible.

Cache


16 kbyte instruction cache with predecode unit, 8 kbyte data cache (Harvard architecture).
Instruction cache: 4-way set-associative, 32 bytes/line, acronym>SI protocol, 2 fetch ports supporting split-line access, 5 predecode bits/byte (10 kbyte), blocking, dual tags, RRR.
Data cache: 4-way set-associative, 32 bytes/line, MESI protocol, dual-ported, blocking, dual tags, write-allocate, 4 banks, RRR.

Architecture


X86 to RISC Operation (ROP) translation.

Superscalar:

  • 5-stage,
  • 3 integer pipelines, 1 FP pipeline.

Dynamic, block oriented, branch prediction with speculative execution.

Physics


Voltage: 3.52 V.

Manufacturing technology: .

  • 3-layer metal, 0.5 micron CMOS (Fab 25, Texas),
  • 0.35 micron CMOS (from Q1 1996).

Packaging: 296 pin SPGA.

Packaging


Packaging:


7.3.1  AMD 5k86 K5 processor

7.3.2  AMD 5k86 SSA/5 processor

7.4  Cyrix 586 processor

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Identification



7.4.1  Cyrix 5x86 processor

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