Advanced Load Address Table (ALAT): between L1 data cache (L1D) and DTLB, keeps track of speculative data loads,
32 entry, two-way set-associative.

Architecture

Double pipeline: 10 stage in-order, 6 instructions wide.
Split issue dispersal: three instructions (16 bytes) per bundle.
Scoreboarding, non-blocking caches (for compile-time non-determinism).

17 execution units:

• 4 Integer units (ALU, Arithmetic Logic Unit),
• 4 Multimedia units (ALU),
• 2 Extended Precision Floating Point (FP) units: F0, F1,
  ANSI/IEEE-754,
  FMAC: Floating Point Multiply Add Calculation: multiply and add of 82 bit floating point values in one cycle (for matrix calculations),
• 2 Single Precision FPUs,
  each executing two calculations per clock,
• all FP units together delivering max. throughput of 6.4 GFLOPS,
• 2 load/store units: M0, M1,
• 3 branch units: B0, B1, B2.

9 issue ports:

• 2 memory: M0, M1,
• 2 integer: I0, I1,
• 2 FP: F0, F1,
• 3 branch: B0, B1, B2,

Dynamic prefetch, branch prediction, speculative execution.

Branch prediction:
512 entry, two-level.
Branch Target Address Cache (BTAC): 64 entry.

Interval Time Counter (ITC): register for timing ticks.
In 32 bit compatibility mode: Time Stamp Counter (TSC).

Streamlined Advanced PIC (SAPIC): based on IA-32 APIC (Advanced Programmable Interrupt Controller),
for Aborts, Interrupts, Faults, and Traps:

• handled by operating system: to Interrupt Vector Address (IVA) through Interrupt Vector Table (IVT),
• handled by PAL firmware.

• 0 - 15: special, high priority,
• 16 - 255: freely assignable.

Virtual address space: 64 bit, no segmentation.
Multiple Address Space (MAS): each process has its own unique Virtual Region (flat linear address space).
8 61 bit Virtual Regions (Virtual Region Number, VRN; Region Identifier, RID), 2²⁴ Virtual Address Spaces of 2⁶¹ bits.
4 kbyte - 256 Mbyte pages (Virtual Page Number, VPN).

Physical address space: 63 bit.
Up to 50 bits supported in page tables.

Write Coalescing (WC): streams of non-cachable writes can be combined into a single bus write transaction.
WC Buffer (WCB): two-entry, 64 byte.

Enhanced Machine Check Architecture (EMCA): parity and ECC (Error-Correcting Code) on all major address and data busses.

44 bit address bus.
Physical addressing:

• 32 bit: 0-4 Gbyte,
• 36 bit: 4-64 Gbyte,
• 44 bit: 64 Gbyte - 16 Tbyte.

133 MHz DDR bus (Merced bus): 64 bit data.
Source Synchronous Signaling (SSS).
2.1 Gbyte/s max. throughput.

Assisted Gunning Transceiver Logic signaling (AGTL+),
based on GTL+ bus of Intel Pentium III and Pentium III Xeon processors.
1.5 V ± 1.5 %.

Power pod connector.

Tests:

• Build-In Self Test (BIST),
• Test Access Port (TAP): IEEE 1149.1 (JTAG),
• In-Target Probe (ITP): debugging interface for board integration,
  JTAG TAP, access to registers, memory, and I/O,
  ITP700 Debug Port (DB): command and control interface for ITP,
  max. 16 MHz,
• Logic Analyzer Interface (LAI),
• code debugging:
  Instruction and Data Breakpoint Registers (IBR, DBR),
  single stepping (through PSR.ss),
  breaks, taken branches (through PSR.tb), privileges,
  instruction and data debugging.

Processor performance monitoring and profiling:

• Performance Monitor Configuration (PMC),
• Performance Monitor Data Registers (PMD),
• 4 32 bit performance counters.

Multi-processing

SMP (Symmetric Multi-Processing): glueless up to four processors (max. 16 in IA-32 compatibility mode).
Shared memory, cache coherency through MESI protocol.

Multiplier

Multiplier (Phase Lock Loop, PLL):
set through pins during reset:

Power management

Power and performance management:
P-states:

• P0: maximum performance, maximum power (highest utilization),
• P15 (lowest utilization),

Performance

Performance:

• slow integer (comparable to X86 processors),
• very fast FP units,
• very slow IA-32 unit,
• L3 cache slow due to small memory bus,

Thermal management

Thermal management: via on-die thermal diode:

• Thermal Alert: thresholds set through SMBus,
  THRMALERT# pin active when threshold crossed,
• no Enhanced Thermal Management (ETM),
• Thermal Trip: processor shutdown when overheated,
  THRMTRIP# pin active, reset processor to resume.

System management

System management: System Management Bus (SMBus):

• Processor Information EEPROM (PIROM): manufacturing and features information,
  permanently write-protected:
  • processor: s-spec / QDF number, sample/production,
  • core: architecture revision, family, model, stepping/revision,
    maximum core frequency, maximum bus frequency, voltage, voltage tolerance,
  • L3 cache: size, voltage, tolerance, stepping,
  • package: cartridge revision, substrate revision,
  • part numbers: processor part number (80542KC),
    processor electronic signature (64 bit serial number),
  • thermal reference,
  • features, IA-32 features, cartridge features,
• scratch EEPROM: for OEM system designer information,
• thermal sensing device (A/D converter), connected to on-die thermal diode.

Marking

Marking:

• Intel brand,
• legal mark,
• product ID,
• Finish Process Order (FPO),
• serial number,
• s-spec,
• country of origin (not for 9000 series),
• Assembly Process Order (APO).

CPUID

CPUID: 8 byte registers:

• registers 0-4: fixed region,
• region 5 and further: variable region.

• registers 0 and 1: vendor id information,
• register 2: ignored,
• register 3: processor implementation information:
  • bits 7:0: largest CPUID register number,
  • bits 15:8: processor revision number,
  • bits 23:16: processor model number,
  • bits 31:24: processor family number (0x07),
  • bits 39:32: processor architecture revision number (0x00),
  • bits 63:40: reserved,
• register 4: processor features:
  • bit 0: long branch instruction (brl) implemented, no need to emulate by operating system,
  • bit 1: spontaneous deferral implemented,
  • bit 2: 16-byte atomic operations implemented,
  • bits 63:3: reserved.

CPUID return values:

Set EAX register to 2, then returned in EAX, EBX, ECX, EDX registers (MSB - LSB):

Market

Used by HP as PA-RISC replacement, and in High Performance Computing (HPC).

Only a few thousand delivered.
Succeeded by Itanium 2 in 2002.

21.1.1  Intel Itanium processor (Merced)

21.2  Intel Itanium 2 processor

Successor of Itanium processor.
Major revision:

• improvements in number of pipeline units, number of clock cycles,
• according to Intel and HP one-and-a-half to two times faster than the Itanium processor,
• brl instruction: 64 bit long branch,
• scoreboarding of multi-cycle instructions, e.g. L1D misses, multimedia, FP.

Compatibility

256 application registers:

• 128 64 bit general purpose registers (integer and multimedia):
  32 general registers (GR0 - GR31): static, available to all programs,
  rest (GR32 - GR127) stacked: available per program,
  managed by Register Stack Engine (RSE) (stack pointer (SP): Current Frame Marker, CFM),
• 128 82 bit floating point registers (FR0 - FR127):
  first 32 registers static: available to all programs,
  rest rotating: can be renamed to accelerate loops.

64 predicate registers (PR0 - PR63): contain predicate test (compare) results, for conditional execution of instructions,
first 16 registers static: available to all programs,
rest rotating: can be renamed to accelerate loops.

8 branch registers (BR0 - BR7).

128 application registers (AR0 - AR127): special-purpose data and control registers.

4 Privilege Levels (PL): 0-3.
Current Privilege Level (CPL) in PSR.cpl (Processor Status Register, PSR).

Bi-endian memory access: controlled by UM.be bit (User Mask, UM).

Memory mapped I/O.

Processor virtualization: enabled by PSR.vm bit, managed by PAL.
Virtual Machine Monitor (VMM): managing and virtualizing system resources, creating a virtual environment.
From Montecito: Intel VT for Itanium (VT-i),
Virtual Processor Descriptor (VPD): description of resources of a single virtual processor,
rest of Virtual Processor State (VPS) maintained by VMM.

IA-32 compatibility mode: IA-32 System Environment, i.e. Pentium III.
16 bit Real Mode, 16 bit VM86, 16/32 bit Protected Mode, memory segmentation.
Multimedia instruction sets: MMX, SSE, SSE2 (from Intel Itanium 2 9000 series processor).
Switch between Itanium and IA-32 instruction sets using JMPE, br.ia, and rtfi.
All interruptions handled by Itanium instruction set code.
Current execution mode in PSR.is.
From Madison, IA-32 support implemented in software, as part of operating system (IA-32 Execution Layer, EL),
IA-32 EL provided by Intel for Linux and Windows,
erratum: segmentation not supported in IA-32 EL versions 4.3, 4.4, 5.3, and 6.5,
erratum: 16 bit application mode not supported in IA-32 EL versions 4.3, 4.4, 5.3, and 6.5,
note: CPUID returns only manufacturer and family of emulated processor model.

PA-RISC supported through Aries emulator.

Operating system: supported through Extensible Firmware Interface (EFI).
System Abstraction Layer (SAL): firmware providing platform initialization, configuration, and test, operating system boot, run-time functionality (i.e. BIOS (Basic Input Output System), Machine Checks, and Platform Management Interruptions (PMI, successor IA-32 System Management Mode (SMM))).
Processor Abstraction Layer (PAL): firmware providing processor specific Machine Checks, initialization, PMI, power management, configuration, and error recovery.

Developer's Interface Guide for IA-64 Servers (DIG64): design guidelines for building blocks and interfaces of IA-64 systems, providing an interoperable and stable baseline hardware interface for software developers.

Cache

On-die L1 cache (Harvard architecture):

• 16 kbyte instruction cache (L1I):
  4-way set-associative, 64 byte line size,
  1 cycle latency,
  32 Gbyte/s max. reading speed.
• 16 kbyte data cache (L1D):
  4-way set-associative, 64 byte line size,
  write-through, no write-allocate,
  1 cycle latency for integers, FPs and semaphores bypass the L1 data cache,
  32 Gbyte/s max. reading speed, 16 Gbyte/s max. writing speed.

On-die, unified L2 cache:
256 kbyte,
8-way set-associative, 128 byte line size,
write back, write-allocate,
non-blocking, out-of-order,
5 cycles minimum latency for integers, 6 cycles minimum latency for FPs,
16 byte banks,
32 Gbyte/s max. reading speed.
Cache coherency through MESI protocol.

From Itanium 2 9000 series processors: on-die L2 cache (Harvard architecture):

• 1 Mbyte instruction cache (L2I):
  8-way set-associative, 128 byte line size,
  7 cycle latency,
• 256 kbyte data cache (L2D):
  8-way set-associative, 128 byte line size,
  write-back, write-allocate,
  non-blocking, out-of-order,
  5 cycles minimum latency for integers, 6 cycles minimum latency for FPs,
  16 byte banks,
  32 Gbyte/s max. reading speed.

On-die, unified L3 cache:
up to 2x 12 = 24 Mbyte,
McKinley and Madison: 4-way set-associative per Mbyte, Madison 9M: 2-way set-associative per Mbyte; 128 byte line size,
fully pipelined, non-blocking,
McKinley: 12 cycles minimum latency for integers, 13 cycles minimum latency for FPs; Madison and Madison 9M: 14 cycles minimum latency for integers, 15 cycles minimum latency for FPs; Montecito: 14 cycles latency,
bandwidth to core 32 bytes per core cycle (256 bit bus to core),
6.2 Gbyte/s max. traffic speed to memory,
providing data to core at up to 48 Gbyte/s.
Cache coherency through MESI protocol,
Intel Cache Safe Technology: protection of data and tags: double bit detection, single bit correction (ECC, Error-Correcting Code).

Translation Look-aside Buffer (TLB) and Virtual Hash Page Table (VHPT):

• Two-level instruction TLB (ITLB): between instruction fetch and decode:
  • L1 ITLB (ITLB1):
    64 entry, fully associative,
    only page size of 4 kbyte supported,
    2 cycles latency,
  • L2 ITLB (ITLB2):
    128 entry, fully associative,
    page size 4 kbyte - 256 Mbyte supported.
• two-level data TLB: between data caches and registers:
  • L1 DTLB (DTLB1):
    32 entry, fully associative,
    2 cycles penalty at miss,
    only page size of 4 kbyte supported,
  • L2 DTLB (DTLB2):
    128 entry, fully associative,
    page size 4 kbyte - 4 Gbyte supported.