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2-issue 5-stage superscalar with 8-stage pipelined FPU (Floating Point Unit).
Intel i80486 CPU upward instruction compatible.
System Management Mode (SMM).
8 kbyte instruction cache, 8 kbyte data cache (Harvard architecture).
Both 2-way set-associative, write-back, no write-allocate.
Branch prediction (BTB: Branch Target Buffer).
32 bit internal data bus (CPU - MMU (Memory Management Unit, including cache))
64 bit external data bus (MMU, including cache - memory).
Separate address space for instructions and data (Harvard architecture).
Parity checking at busses.
Upgrading: adding another Intel Pentium CPU.
FDIV bug: In October 1994, Dr. Thomas R. Nicely, then Professor of Mathematics at the Lynchburg College, Lynchburg, Virginia, reported a bug present in the FPU of all Intel Pentium CPUs. The double precision part of the mantissa is not computed correctly when dividing in some areas of the mantissa space of the divisor. The bug is fixed in Intel Pentium CPUs produced after November 1994.
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