The ChipList, by Adrian Offerman; The Processor Portal

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3DNow! Instruction Set Architecture (ISA) Extension

3DNow! instructions added with the K6-2 processors:

  • FEMMS
    Fast Exit Multimedia State
  • PAVGUSB
    Packed Average Unsigned Bytes
  • PF2ID
    Packed Floating-Point to Integer Doubleword Converson
  • PFACC
    Packed Floating-Point Accumulate
  • PFADD
    Packed Floating-Point Add
  • PFCMPEQ
    Packed Floating-Point Compare Equal
  • PFCMPGE
    Packed Floating-Point Compare Greater or Equal
  • PFCMPGT
    Packed Floating-Point Compare Greater Than
  • PFMAX
    Packed Single-Precision Floating-Point Maximum
  • PFMIN
    Packed Single-Precision Floating-Point Minimum
  • PFMUL
    Packed Floating-Point Multiply
  • PFRCP
    Floating-Point Reciprocal Approximation
  • PFRCPIT1
    Packed Floating-Point Reciprocal Iteration 1
  • PFRCPIT2
    Packed Floating-Point Reciprocal or Reciprocal Square Root Iteration 2
  • PFRSQIT1
    Packed Floating-Point Reciprocal Square Root Iteration 1
  • PFRSQRT
    Packed Floating-Point Reciprocal Square Root Approximation
  • PFSUB
    Packed Floating-Point Subtract
  • PFSUBR
    Packed Floating-Point Subtract Reverse
  • PI2FD
    Packed Integer to Floating-Point Doubleword Conversion
  • PMULHRW
    Packed Multiply High Rounded Word
  • PREFETCH/PREFETCHW
    Prefetch L1 Data-Cache Line