The ChipList, by Adrian Offerman; The Processor Portal

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19.8.2  Intel Celeron E1xxx series Dual-Core processor (Allendale-512)

Identification


Model name: Celeron E1xxx series Dual-Core.
Code name: Allendale-512.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 512 kbyte.

Architecture


200 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Halt state (C1), Stop-Grant state,
  • Enhanced Halt state (C1E).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
200/1600 MHz Intel Celeron E1200 Dual-Core CPU 8 January 2008 OEM: HH80557PG025D,
PIB: BX80557E1200,
PIB: BXC80557E1200F
200/2000 MHz Intel Celeron E1400 Dual-Core CPU 10 April 2008 OEM: HH80557PG041D,
PIB: BX80557E1400,
PIB: BXC80557E1400

Physics


Voltage: 1.162-1.312 V.
Power dissipation: 65 W TDP.

Temperature: 5-73.3 °C.

Manufacturing process: 65 nm (P1264).

Packaging: Socket T / LGA 775.

Thermal management


Thermal management:

  • TM2 (Thermal Monitor).

System management


No remote management.

Marking


Platform Compatibility Guide (PCG): 06.

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xD stepping M0

Step level


Text:

Step levels: M0.

S-Spec / Stepping code


Model Code Stepping
Intel Celeron E1200 Dual-Core CPU SLAQW M0
Intel Celeron E1400 Dual-Core CPU SLAR2 M0

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