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19.13.2  Intel Core 2 Quad Xeon DP LV L53xx series processor (Cloverton LV)

Identification


Model name: Core 2 Quad Xeon DP LV L53xx series.
Code name: Cloverton LV.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Symmetric Multi-Processing (SMP): max. 2-way.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction
266/1600 MHz Intel Core 2 Quad-Core Xeon DP LV L5310 CPU 6 March 2007
266/1866 MHz Intel Core 2 Quad-Core Xeon DP LV L5320 CPU 7 March 2007
333/2000 MHz Intel Core 2 Quad-Core Xeon DP LV L5335 CPU 6 August 2007

Physics


Power dissipation: 50 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket J / LGA 771.

System management


Remote management: Intel Active Management (iAMT2).

Step level


Text:

Step levels: B3.

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