The ChipList, by Adrian Offerman; The Processor Portal

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19.5.1  Intel (Mobile) Celeron M 5x0-fused series processor (Merom-1024)

Identification


Model name: (Mobile) Celeron M 5x0-fused series.
Code name: Merom-1024.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Single core (other core disfunctional/disabled).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 1 Mbyte (other 3 Mbyte disfunctional/disabled).

Architecture


133 MHz QDR bus.

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Single core (other core disfunctional/disabled).

Multiplier


Power management


Power management:

  • no Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
133/1600 MHz Intel Celeron M 520-fused CPU 12 January 2007 OEM: LF80537NE0251M,
PIB: BX80537520
133/1733 MHz Intel Celeron M 530-fused CPU 13 March 2007 OEM: LF80537NE0301M,
PIB: BX80537530

Physics


Voltage: 0.95-1.30 V.
Power dissipation: 30 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket M.

System management


No remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2

Step level


Text:

Step levels: B2.

S-Spec / Stepping code


Model Code Stepping
Intel Celeron M 520-fused CPU QVMC B2 ES
Intel Celeron M 520-fused CPU SL9WT B2

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