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21.1.1  Intel Itanium processor (Merced)

Identification


Model name: Itanium.
Code name: Merced.
Family name: Itanium Processor Family (IPF).
Supplier: Intel.
Component class: CPU.

Generation


Generation: Itanium.

Compatibility


Bi-endian memory access.

Processor virtualization.

IA-32 compatibility mode: IA-32 System Environment.
16 bit Real Mode, 16 bit VM86, 16/32 bit Protected Mode, memory segmentation.
Multimedia instruction sets: MMX, SSE.

PA-RISC supported through Aries emulator.

Extensible Firmware Interface (EFI).
System Abstraction Layer (SAL).
Processor Abstraction Layer (PAL).

Cache


On-die L1 cache (Harvard architecture):

  • 16 kbyte instruction cache,
  • 16 kbyte data cache.

On-die, unified L2 cache: 96 kbyte.

L3 cache: 2 or 4 Mbyte, apart in package, connected through Front Side Bus (FSB).

Architecture


Virtual address space: 64 bit, no segmentation.
Multiple Address Space (MAS): each process has its own unique Virtual Region (flat linear address space).
8 61 bit Virtual Regions, 224 Virtual Address Spaces of 261 bits.
4 kbyte - 256 Mbyte pages.

Physical address space: 63 bit.
Up to 50 bits supported in page tables.

Write Coalescing (WC): streams of non-cachable writes can be combined into a single bus write transaction.
WC Buffer (WCB): two-entry, 64 byte.

Parity and ECC (Error-Correcting Code) on all major address and data busses.

44 bit address bus.
Physical addressing:

  • 32 bit: 0-4 Gbyte,
  • 36 bit: 4-64 Gbyte,
  • 44 bit: 64 Gbyte - 16 Tbyte.
Virtual addressing: 54 bit.
Page sizes: 4 kbyte - 256 Mbyte.

133 MHz DDR bus (Merced bus): 64 bit data.

Multi-processing


SMP (Symmetric Multi-Processing): glueless up to four processors (max. 16 in IA-32 compatibility mode).
Only one step level difference between processors verified,
stepping C2 not verified with other step levels.

Multiplier


Multiplier: 2/11, 2/12.

Power management


Power and performance management: P-states.

Clock speed


Clock speed Model Cache Multiplier Power dissipation Introduction
133/733 MHz Intel Itanium 733 2MB CPU 2 Mbyte L3 5.5 116.0 W TDP June 2001
133/733 MHz Intel Itanium 733 4MB CPU 4 Mbyte L3 5.5 130.0 W TDP June 2001
133/800 MHz Intel Itanium 800 2MB CPU 2 Mbyte L3 6 116.0 W TDP June 2001
133/800 MHz Intel Itanium 800 4MB CPU 4 Mbyte L3 6 130.0 W TDP June 2001

Physics


Power dissipation:

  • 2 Mbyte L3 cache: 116 W TDP,
  • 4 Mbyte L3 cache: 130 W TDP.

Manufacturing process: 180 nm.

Number of transistors: 25 million in CPU, 300 million in L3 cache.

Die size: 300 mm2.

Packaging: PAC418.

Thermal management


Thermal management:

  • Thermal Alert,
  • no Enhanced Thermal Management (ETM),
  • Thermal Trip.

System management


System management: System Management Bus (SMBus).

Step level


Text:

Step levels: C0, C1, C2.

S-Spec / Stepping code


Code Stepping CPUID Clock speed Description
SL4LT C0 0007000604 133/733 MHz 2 Mbyte L3 cache
SL4LS C0 0007000604 133/733 MHz 4 Mbyte L3 cache
SL4LR C0 0007000604 133/800 MHz 2 Mbyte L3 cache
SL4LQ C0 0007000604 133/800 MHz 4 Mbyte L3 cache
SL5VS C1 0007000704 133/733 MHz 2 Mbyte L3 cache
SL5VT C1 0007000704 133/733 MHz 4 Mbyte L3 cache
SL5VU C1 0007000704 133/800 MHz 2 Mbyte L3 cache
SL5VW C1 0007000704 133/800 MHz 4 Mbyte L3 cache
Code Stepping CPUID Clock speed Description
SL6RH C2 0007000804 133/733 MHz 2 Mbyte L3 cache
SL6RK C2 0007000804 133/800 MHz 2 Mbyte L3 cache
SL6RL C2 0007000804 133/800 MHz 4 Mbyte L3 cache

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