The ChipList, by Adrian Offerman; The Processor Portal

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15.5.4  AMD Mobile Sempron processor (Sonora, revision D0, Low Power)

Identification


Model name: Mobile Sempron.
Code name: Sonora, revision D0, Low Power.
Family name: Cities.
Supplier: AMD.
Component class: CPU.

Generation


Generation: K8.

Compatibility


No 64 bit technology: AMD64.

Multimedia instruction sets: MMX, Enhanced 3DNow!, SSE, SSE2.

Cache


L1 cache: 64 kbyte instruction cache, 64 kbyte data cache (Harvard architecture).
L2 cache: 256 kbyte (other 256 kbyte disfunctional/disabled) or 128 kbyte (other 384 kbyte disfunctional/disabled).

Architecture


64 bit, 200 MHz, DDR memory controller: max. 4 x 512 Mbyte = 2 Gbyte (2 x 1 Gbyte double-sided PC3200 memory module).

800 MHz HyperTransport bus.

Memory protection: NX bit (Enhanced Virus Protection, EVP).

Multiplier


Power management


Power management: PowerNow!.

Clock speed


Clock speed Model Cache Multiplier Introduction Order part numbers
200 MHz / 1.60 GHz AMD Mobile Sempron 2600+ CPU 128 kbyte L2 8 July 2004 OEM: SMS2600BOX2LB
200 MHz / 1.60 GHz AMD Mobile Sempron 2800+ CPU 256 kbyte L2 8 July 2004 OEM: SMS2800BOX3LB
200 MHz / 1.80 GHz AMD Mobile Sempron 3000+ CPU 128 kbyte L2 9 November 2004 OEM: SMS3000BOX2LB
200 MHz / 1.80 GHz AMD Mobile Sempron 3100+ CPU 256 kbyte L2 9 January 2005 OEM: SMS3100BOX3LB

Physics


Voltage: 0.975-1.250 V.
Power dissipation: 25 W TDP.

Temperature: max. 95 °C.

Manufacturing process: 90 nm.

Number of transistors: 68.5 million.

Die size: 84 mm2.

Packaging: Socket 754.

Step level


Text:

Step levels: D0.

S-Spec / Stepping code


Model Code Stepping
AMD Mobile Sempron 3100+ CPU ABBGD D0
AMD Mobile Sempron 3000+ CPU CBBFD D0
AMD Mobile Sempron 2600+ CPU CBBHD D0
AMD Mobile Sempron 2800+ CPU CBBID D0
AMD Mobile Sempron 2800+, 3100+ CPU LBBID D0

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