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19  Intel Core 2 processors

Overview


Intel Core 2 processor overview Core 2 Core 2 Duo Conroe Conroe 2M Allendale Core 2 Quad Kentsfield Core 2 Duo Merom Merom 2M Celeron M Merom-1024 Core 2 Extreme Conroe XE Core 2 Quad Extreme Kentsfield XE Core 2 Xeon Woodcrest Woodcrest LV Conroe Conroe 2M Core 2 Quad Xeon Cloverton Cloverton LV Kentsfield Quad-Core Xeon MP Tigerton Tigerton LV Dual-Core Xeon MP Tigerton-DC

Compatibility


System Management Mode (SMM).


19.1  Intel Core 2 Duo processor


19.1.1  Intel Core 2 Duo E6xxx series processor (Conroe)

Identification


Model name: Core 2 Duo E6xxx series.
Code name: Conroe.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E),
  • stepping G0: Extended Stop Grant State (C2E).

Clock speed


Clock speed Model Multiplier Voltage Temperature Introduction Order part numbers
266/1866 MHz Intel Core 2 Duo E6320 CPU 7 0.187-1.325 V 5-60.1 °C April 2007 OEM (stepping B2): HH80557PH0364M,
PIB (stepping B2): BX80557E6320
266/2133 MHz Intel Core 2 Duo E6420 CPU 8 0.187-1.325 V 5-60.1 °C April 2007 OEM (stepping B2): HH80557PH0464M,
PIB (stepping B2): BX80557E6420
333/2333 MHz Intel Core 2 Duo E6540 1 CPU 7 0.962-1.350 V 5-72 °C July 2007 OEM (stepping G0): HH80557PJ0534M
333/2333 MHz Intel Core 2 Duo E6550 CPU 7 0.962-1.350 V 5-72 °C July 2007 OEM (stepping G0): HH80557PJ0534MG,
PIB (stepping G0): BX80557E6550,
PIB (stepping G0): BX80557E6550R
266/2400 MHz Intel Core 2 Duo E6600 CPU 9 0.850-1.3525 V 5-60.1 °C July 2006 OEM (stepping B2): HH80557PH0564M,
PIB (stepping B2): BX80557E6600
266/2667 MHz Intel Core 2 Duo E6700 CPU 10 0.850-1.3525 V 5-60.1 °C July 2006 OEM (stepping B2): HH80557PH0674M,
PIB (stepping B2): BX80557E6700
333/2667 MHz Intel Core 2 Duo E6750 CPU 8 0.962-1.350 V 5-72 °C July 2007 OEM (stepping G0): HH80557PJ0674MG,
PIB (stepping G0): BX80557E6750
333/3000 MHz Intel Core 2 Duo E6850 CPU 9 0.962-1.350 V 5-72 °C July 2007 OEM (stepping G0): HH80557PJ0804MG,
PIB (stepping G0): BX80557E6850

  1. no Trusted Execution Technology (TXT).

Physics


Power dissipation: 65 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels: B2, G0.

S-Spec / Stepping code


Model Code Stepping Description Introduction
Intel Core 2 Duo E6700 CPU SL9S7 B2    
Intel Core 2 Duo E6600 CPU SL9S8 B2    
Intel Core 2 Duo E6700 CPU SL9ZF B2 Extended HALT power specification reduced from 20-22 W to 12 W December 2006
Intel Core 2 Duo E6600 CPU SL9ZL B2 Extended HALT power specification reduced from 20-22 W to 12 W December 2006
Intel Core 2 Duo E6420 CPU SLA4T B2    
Intel Core 2 Duo E6320 CPU SLA4U B2    
Intel Core 2 Duo E6850 CPU SLA9U G0    
Intel Core 2 Duo E6750 CPU SLA9V G0    
Model Code Stepping Description Introduction
Intel Core 2 Duo E6550 CPU SLA9X G0    
Intel Core 2 Duo E6540 CPU SLAA5 G0    

19.1.2  Intel Core 2 Duo E6xxx series processor (Conroe, 2 Mbyte L2 cache)

Identification


Model name: Core 2 Duo E6xxx series.
Code name: Conroe, 2 Mbyte L2 cache.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte (other 2 Mbyte disfunctional/disabled).

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/1866 MHz Intel Core 2 Duo E6300 CPU 7 July 2006 OEM: HH80557PH0362M,
PIB: BX80557E6300
266/2133 MHz Intel Core 2 Duo E6400 CPU 8 July 2006 OEM: HH80557PH0462M,
PIB: BX80557E6400

Physics


Voltage: 0.85-1.3525 V.
Power dissipation: 65 W TDP.

Temperature: 5-60.1 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2

Step level


Text:

Step levels: B2.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Duo E6400 CPU SL9S9 B2
Intel Core 2 Duo E6300 CPU SL9SA B2

19.1.3  Intel Core 2 Duo E6xxx series processor (Allendale)

Identification


Model name: Core 2 Duo E6xxx series.
Code name: Allendale.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/1866 MHz Intel Core 2 Duo E6300 CPU 7 January 2007 OEM: HH80557PH0362M,
PIB: BX80557E6300
266/2133 MHz Intel Core 2 Duo E6400 CPU 8 January 2007 OEM: HH80557PH0462M,
PIB: BX80557E6400

Physics


Voltage: 1.225-1.325 V.
Power dissipation: 65 W TDP.

Temperature: 5-61.4 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 167 million.

Die size: 111 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x2 stepping L2

Step level


Text:

Step levels:

  • L2: Extended HALT power specification reduced from 22 W to 12 W.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Duo E6400 CPU QUHB L2 QS
Intel Core 2 Duo E6400 CPU SL9T9 L2
Intel Core 2 Duo E6300 CPU QUHG L2 QS
Intel Core 2 Duo E6300 CPU SL9TA L2

19.1.4  Intel Core 2 Duo E4xxx series processor (Allendale)

Identification


Model name: Core 2 Duo E4xxx series.
Code name: Allendale.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte.

Architecture


200 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E),
  • E4500: Extended Stop Grant State (C2E).

Clock speed


Clock speed Model Multiplier Voltage Introduction Order part numbers
200/1800 MHz Intel Core 2 Duo E4300 CPU 9 1.225-1.325 V January 2007 OEM (stepping L2): HH80557PG0332M,
PIB (stepping L2): BX80557E4300
200/2000 MHz Intel Core 2 Duo E4400 CPU 10 stepping L2: 1.162-1.312 V,
stepping M0: 0.962-1.325 V
April 2007 OEM (stepping L2, M0): HH80557PG0412M,
PIB (stepping L2, M0): BX80557E4400
200/2200 MHz Intel Core 2 Duo E4500 1 CPU 11 0.962-1.325 V July 2007 OEM (stepping M0): HH80557PG0492M,
PIB (stepping M0): BX80557E4500
200/2400 MHz Intel Core 2 Duo E4600 CPU 12 1.162-1.312 V October 2007 OEM (stepping M0): HH80557PG0562M,
PIB (stepping M0): BX80557E4600
200/2600 MHz Intel Core 2 Duo E4700 CPU 13 1.162-1.312 V March 2008 OEM (stepping G0): HH80557PG0642M,
PIB (stepping G0): BXC80557E4700,
PIB (stepping G0): BX80557E4700

  1. Extended Stop Grant State (C2E) supported

Physics


Power dissipation: 65 W TDP.

Temperature:

  • stepping L2: 5-61.4 °C,
  • stepping M0: 5-73.3 °C,
  • stepping G0: 5-73.3 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 167 million.

Die size: 111 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x2 stepping L2
0x0 0x6 0xF 0xD stepping M0
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels:

  • L2: Extended HALT power specification reduced from 22 W to 12 W,
  • M0 (July 22, 2007): Extended HALT power specification reduced from 12 W to 8 W,
  • G0.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Duo E4300 CPU SL9TB L2 PCG: 06
Intel Core 2 Duo E4400 CPU SLA3F L2 PCG: 06
Intel Core 2 Duo E4600 CPU SLA94 M0 PCG: 06
Intel Core 2 Duo E4500 CPU SLA95 M0 PCG: 06
Intel Core 2 Duo E4400 CPU SLA98 M0 PCG: 06
Intel Core 2 Duo E4700 CPU Q5UX G0 ES  
Intel Core 2 Duo E4700 CPU SLALT G0 PCG: 06

19.1.5  Intel Core 2 Duo E8xxx series processor (Wolfdale)

Identification


Model name: Core 2 Duo E8xxx series.
Code name: Wolfdale.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3. SSSE3, SSE4.1.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 6 Mbyte.

Architecture


333 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E),
  • Extended Stop Grant State (C2E),
  • Extended State (C4).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
333/2.66 GHz Intel Core 2 Duo E8190 1 CPU 8 January 2007 OEM: EU80570PJ0676MN
333/2.66 GHz Intel Core 2 Duo E8200 CPU 8 January 2007 OEM: EU80570PJ0676M,
PIB: BX80570E8200,
PIB: BXC80570E8200
333/2.83 GHz Intel Core 2 Duo E8300 CPU 8.5 April 2008 OEM: EU80570AJ0736M
333/3.00 GHz Intel Core 2 Duo E8400 CPU 9 January 2007 OEM: EU80570PJ0806M,
PIB: BX80570E8400,
PIB: BXC80570E8400
333/3.16 GHz Intel Core 2 Duo E8500 CPU 9.5 January 2007 OEM: EU80570PJ0876M,
PIB: BX80570E8500,
PIB: BXC80570E8500

  1. no Virtualization Technology (VT); no Trusted Execution Technology (TXT).

Physics


Voltage: 1.15-1.225 V (0.850-1.3625 V).
Power dissipation: 65 W TDP.

Temperature: max. 72.4 °C.

Manufacturing process: 45 nm (P1266).

Number of transistors: 410 million.

Die size: 107 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping C0

Step level


Text:

Step levels: C0.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Duo E8300 CPU SLAPJ C0 PCG: 06
Intel Core 2 Duo E8500 CPU SLAPK C0 PCG: 06
Intel Core 2 Duo E8400 CPU SLAPL C0 PCG: 06
Intel Core 2 Duo E8200 CPU SLAPP C0 PCG: 06
Intel Core 2 Duo E8190 CPU SLAQR C0 PCG: 05A

19.1.6  Intel Core 2 Duo E7xxx series processor (Wolfdale-3M)

Identification


Model name: Core 2 Duo E7xxx series.
Code name: Wolfdale-3M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3. SSSE3, SSE4.1.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 3 Mbyte (other 3 Mbyte disfunctional/disabled).

Architecture


266 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E),
  • no Extended Stop Grant State (C2E),
  • no Extended State (C4).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/2533 GHz Intel Core 2 Duo E7200 CPU 9.5 April 2008 OEM: EU80571PH0613M,
PIB: BXC80571E7200,
PIB: BX80571E7200

Physics


Voltage: 0.850-1.3625 V.
Power dissipation: 65 W TDP.

Temperature: max. 74.1 °C.

Manufacturing process: 45 nm (P1266).

Number of transistors: 410 million.

Die size: 107 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping M0

Step level


Text:

Step levels: M0.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Duo E7200 CPU SLAPC M0 PCG: 06
Intel Core 2 Duo E7200 CPU SLAVN M0 PCG: 06

19.2  Intel Core 2 Duo mobile processor


19.2.1  Intel Core 2 Duo T7xxx series mobile processor (Merom, Socket M)

Identification


Model name: Core 2 Duo T7xxx series.
Code name: Merom, Socket M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


166 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
166/2000 MHz Intel Core 2 Duo T7200 CPU 12 August 2006 OEM (BGA): LE80537GF0414M,
OEM (PGA): LF80537GF0414M,
PIB (PGA): BX80537T7200
166/2166 MHz Intel Core 2 Duo T7400 CPU 13 August 2006 OEM (BGA): LE80537GF0484M,
OEM (PGA): LF80537GF0484M,
PIB (PGA): BX80537T7400
166/2333 MHz Intel Core 2 Duo T7600 CPU 14 August 2006 OEM (BGA): LE80537GF0534M,
OEM (PGA): LF80537GF0534M,
PIB (PGA): BX80537T7600

Physics


Voltage: (1.0375-1.30 V).
Power dissipation: 34 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket M.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2

Step level


Text:

Step levels: B2.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Duo T7600 CPU SL9SD B2 Socket M (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7400 CPU SL9SE B2 Socket M (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7200 CPU SL9SF B2 Socket M (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7600 CPU SL9SJ B2 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7400 CPU SL9SK B2 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7200 CPU SL9SL B2 FCBGA6/Micro-FCBGA

19.2.2  Intel Core 2 Duo T5xxx series mobile processor (Merom, 2 Mbyte L2 cache, Socket M)

Identification


Model name: Core 2 Duo T5xxx series.
Code name: Merom, 2 Mbyte L2 cache, Socket M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte (other 2 Mbyte disfunctional/disabled).

Architecture


133/166 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Voltage interval Introduction Order part numbers
133/1600 MHz Intel Core 2 Duo T5200 1 2 CPU 12 1.075-1.250 V October 2006 OEM (PGA): LF80537GE0251M
166/1667 MHz Intel Core 2 Duo T5500 1 CPU 10 1.0375-1.30 V August 2006 OEM (BGA): LE80537GF0282M,
OEM (PGA): LF80537GF0282M,
PIB (PGA): BX80537T5500
166/1833 MHz Intel Core 2 Duo T5600 CPU 11 1.0375-1.30 V August 2006 OEM (BGA): LE80537GF0342M,
OEM (PGA): LF80537GF0342M,
PIB (PGA): BX80537T5600

  1. no Virtualization Technology (VT)
  2. OEM only

Physics


Voltage: (1.0375-1.30 V).
Power dissipation: 34 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket M.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2

Step level


Text:

Step levels: B2.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Duo T5600 CPU SL9SG B2 Socket M (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T5500 CPU SL9SH B2 Socket M (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T5600 CPU SL9SP B2 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T5500 CPU SL9SQ B2 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T5200 CPU SL9VP B2 Socket M (FCPGA6/Micro-FCPGA)

19.2.3  Intel Core 2 Duo T7xxx series mobile processor (Merom, Socket P)

Identification


Model name: Core 2 Duo T7xxx series.
Code name: Merom, Socket P.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


100-200 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
200/2000 MHz Intel Core 2 Duo T7300 CPU 10 May 2007 OEM (BGA, stepping E1): LE80537GG0414M,
OEM (PGA, stepping E1): LF80537GG0414M,
PIB (PGA, stepping E1): BX80537T7300
200/2200 MHz Intel Core 2 Duo T7500 CPU 11 May 2007 OEM (BGA, stepping E1, G0): LE80537GG0494M,
OEM (PGA, stepping E1, G0): LF80537GG0494M,
PIB (PGA, stepping E1, G0): BX80537T7500
200/2400 MHz Intel Core 2 Duo T7700 CPU 12 May 2007 OEM (BGA, stepping E1, G0): LE80537GG0564M,
OEM (PGA, stepping E1, G0): LF80537GG0564M,
PIB (PGA, stepping E1, G0): BX80537T7700
200/2600 MHz Intel Core 2 Duo T7800 CPU 13 September 2007 OEM (BGA, stepping G0): LE80537GG0644M,
OEM (PGA, stepping G0): LF80537GG0644ML,
PIB (PGA, stepping G0): BX80537T7800

Physics


Voltage: (1.0375-1.30 V).
Power dissipation: 34 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket P.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xA stepping E1
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels:

  • E1,
  • G0 (September 2, 2007).

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Duo T7700 CPU SLA3M E1 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7500 CPU SLA3N E1 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7300 CPU SLA3P E1 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7700 CPU SLA43 E1 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7500 CPU SLA44 E1 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7300 CPU SLA45 E1 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7800 CPU SLA75 G0 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7700 CPU SLADL G0 FCBGA6/Micro-FCBGA
Model Code Stepping Description
Intel Core 2 Duo T7500 CPU SLADM G0 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7800 CPU SLAF6 G0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7700 CPU SLAF7 G0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7500 CPU SLAF8 G0 Socket P (FCPGA6/Micro-FCPGA)

19.2.4  Intel Core 2 Duo LV L7xxx series mobile processor (Merom LV)

Identification


Model name: Core 2 Duo LV L7xxx series.
Code name: Merom LV.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


166 MHz or 100-200 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
166/1333 MHz Intel Core 2 Duo LV L7200 CPU 8 Q1 2007 OEM (stepping B2): LE80537LF0144M
200/1400 MHz Intel Core 2 Duo LV L7300 CPU 7 May 2007 OEM (stepping E1): LE80537LG0174M
166/1500 MHz Intel Core 2 Duo LV L7400 CPU 9 Q1 2007 OEM (stepping B2): LE80537LF0214M
200/1600 MHz Intel Core 2 Duo LV L7500 CPU 8 May 2007 OEM (stepping E1, G0): LE80537LG0254M
200/1800 MHz Intel Core 2 Duo LV L7700 CPU 9 September 2007 OEM (stepping G0)

Physics


Voltage:

  • stepping B2: 0.975-1.062 V (0.90-1.10 V),
  • stepping E1, G0: 0.975-1.062 V (0.90-1.20 V),

Power dissipation: 17 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: FCBGA6.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2
0x0 0x6 0xF 0xA stepping E1
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels:

  • B2,
  • E1,
  • G0 (September 2, 2007).

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Duo LV L7400 CPU SL9SM B2
Intel Core 2 Duo LV L7200 CPU SL9SN B2
Intel Core 2 Duo LV L7500 CPU SLA3R E1
Intel Core 2 Duo LV L7300 CPU SLA3S E1
Intel Core 2 Duo LV L7700 CPU   G0
Intel Core 2 Duo LV L7500 CPU QXMV G0 QS
Intel Core 2 Duo LV L7500 CPU SLAET G0

19.2.5  Intel Core 2 Duo T5xxx series mobile processor (Merom 2M, Socket M)

Identification


Model name: Core 2 Duo T5xxx series.
Code name: Merom 2M, Socket M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte.

Architecture


133/166 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Voltage interval Introduction Order part numbers
133/1733 MHz Intel Core 2 Duo T5300 1 2 CPU 13 1.075-1.250 V Q1 2007 OEM (PGA): LF80537GE0302M
166/1667 MHz Intel Core 2 Duo T5500 CPU 10 1.0375-1.30 V January 2007 OEM (BGA): LE80537GF0282M,
OEM (PGA): LF80537GF0282M,
PIB (PGA): BX80537T5500
166/1833 MHz Intel Core 2 Duo T5600 CPU 11 1.0375-1.30 V January 2007 OEM (BGA): LE80537GF0342M,
OEM (PGA): LF80537GF0342M,
PIB (PGA): BX80537T5600

  1. no Virtualization Technology (VT)
  2. OEM only

Physics


Voltage: (1.0375-1.30 V).
Power dissipation: 34 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 167 million.

Die size: 111 mm2.

Packaging: Socket M.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x2 stepping L2

Step level


Text:

Step levels: L2.

S-Spec / Stepping code


Model Code Stepping Description Introduction
Intel Core 2 Duo T5600 CPU QUFU L2 QS Socket M (FCPGA6/Micro-FCPGA) November 2006
Intel Core 2 Duo T5600 CPU SL9U3 L2 Socket M (FCPGA6/Micro-FCPGA) January 2007
Intel Core 2 Duo T5500 CPU QUGG L2 QS Socket M (FCPGA6/Micro-FCPGA) November 2006
Intel Core 2 Duo T5500 CPU SL9U4 L2 Socket M (FCPGA6/Micro-FCPGA) January 2007
Intel Core 2 Duo T5600 CPU QUGK L2 QS FCBGA6/Micro-FCBGA November 2006
Intel Core 2 Duo T5600 CPU SL9U7 L2 FCBGA6/Micro-FCBGA January 2007
Intel Core 2 Duo T5500 CPU QUGO L2 QS FCBGA6/Micro-FCBGA November 2006
Intel Core 2 Duo T5500 CPU SL9U8 L2 FCBGA6/Micro-FCBGA January 2007
Model Code Stepping Description Introduction
Intel Core 2 Duo T5300 CPU SL9WE L2 Socket M (FCPGA6/Micro-FCPGA)  

19.2.6  Intel Core 2 Duo T5xxx/T7xxx series mobile processor (Merom 2M, Socket P)

Identification


Model name: Core 2 Duo T5xxx/T7xxx series.
Code name: Merom 2M, Socket P.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte.

Architecture


100-166/200 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

T7xxx series: Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Voltage Introduction Order part numbers
166/1500 MHz Intel Core 2 Duo T5250 1 2 CPU 9 1.0375-1.3000 V Q2 2007 OEM (PGA): LF80537GF0212M
200/1400 MHz Intel Core 2 Duo T5270 1 2 CPU 7 1.0375-1.3000 V October 2007  
166/1667 MHz Intel Core 2 Duo T5450 1 2 CPU 10 1.0375-1.3000 V Q2 2007 OEM (PGA): LF80537 T5450
200/1600 MHz Intel Core 2 Duo T5470 1 2 CPU 8 1.0375-1.3000 V July 2007 OEM (PGA): LF80537 T5470
166/1833 MHz Intel Core 2 Duo T5550 1 2 CPU 11 1.075-1.175 V January 2008 OEM (PGA): LF80537GF0342MT
166/2000 MHz Intel Core 2 Duo T5750 1 2 CPU 12 1.0375-1.3000 V January 2008  
166/2167 MHz Intel Core 2 Duo T5850 1 2 CPU 13   March 2008  
200/1800 MHz Intel Core 2 Duo T7100 CPU 9 1.075-1.175 V May 2007 OEM (BGA): LE80537GG0332M,
OEM (PGA): LF80537GG0332M,
PIB (PGA): BX80537T7100
Clock speed Model Multiplier Voltage Introduction Order part numbers
200/2000 MHz Intel Core 2 Duo T7250 CPU 10 1.075-1.175 V September 2007 OEM (BGA): LE80537GG0412M,
OEM (PGA): LF80537GG0412M,
PIB (PGA): BX80537T7250

  1. no Virtualization Technology (VT)
  2. OEM only

Physics


Power dissipation: 35 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 167 million.

Die size: 111 mm2.

Packaging: Socket P.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xD stepping M0

Step level


Text:

Step levels: M0.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Duo T7250 CPU SLA3T M0 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7100 CPU SLA3U M0 FCBGA6/Micro-FCBGA
Intel Core 2 Duo T7250 CPU SLA49 M0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T7100 CPU SLA4A M0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T5750 CPU   M0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T5550 CPU SLA4E M0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T5450 CPU SLA4F M0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T5250 CPU SLA9S M0 Socket P (FCPGA6/Micro-FCPGA)
Model Code Stepping Description
Intel Core 2 Duo T5470 CPU SLAEB M0 Socket P (FCPGA6/Micro-FCPGA)
Intel Core 2 Duo T5270 CPU   M0 Socket P (FCPGA6/Micro-FCPGA)

19.2.7  Intel Core 2 Duo ULV U7xxx series mobile processor (Merom 2M ULV)

Identification


Model name: Core 2 Duo ULV U7xxx series.
Code name: Merom 2M ULV.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte.

Architecture


133 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
133/1066 MHz Intel Core 2 Duo ULV U7500 CPU 8 April 2007 OEM (stepping L2, M0): LE80537UE0042M
133/1200 MHz Intel Core 2 Duo ULV U7600 CPU 9 April 2007 OEM (stepping L2, M0): LE80537UE0092M
133/1333 MHz Intel Core 2 Duo ULV U7700 CPU 10 December 2007 OEM (stepping M0)

Physics


Voltage: 0.80-0.975 V.
Power dissipation: 10 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 167 million.

Die size: 111 mm2.

Packaging: FCBGA6.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x2 stepping L2
0x0 0x6 0xF 0xD stepping M0

Step level


Text:

Step levels:

  • L2,
  • M0 (Q3 2007).

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Duo ULV U7600 CPU SLA2U L2
Intel Core 2 Duo ULV U7500 CPU SLA2V L2
Intel Core 2 Duo ULV U7700 CPU SLV3V M0
Intel Core 2 Duo ULV U7600 CPU SLV3W M0
Intel Core 2 Duo ULV U7500 CPU SLV3X M0

19.2.8  Intel Core 2 Duo T9xxx series mobile processor (Penryn)

Identification


Model name: Core 2 Duo T9xxx series.
Code name: Penryn.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 6 Mbyte.

Architecture


100-200 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Intel Dynamic Acceleration (IDA): while running extended serial code, one core can temporary run at a higher frequency while the other is turned off, so the total power dissipation stays within the operating limits.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
200/2500 MHz Intel Core 2 Duo T9300 CPU 12.5 January 2008 OEM (BGA): EC80576GG0606M,
OEM (PGA): FF80576GG0606M,
PIB (PGA): BX80576T9300
200/2600 MHz Intel Core 2 Duo T9500 CPU 13 January 2008 OEM (BGA): EC80576GG0646M,
OEM (PGA): FF80576GG0646M

Physics


Voltage:

  • s-spec SLAPV, SLAPW: (1.00-1.250 V),
  • others: (1.062-1.150 V).

Power dissipation: 35 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 45 nm (P1266).

Number of transistors: 410 million.

Die size: 110 mm2.

Packaging: Socket P.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping C0

Step level


Text:

Step levels: C0.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Duo T9300 CPU SLAPV C0
Intel Core 2 Duo T9500 CPU SLAPW C0
Intel Core 2 Duo T9300 CPU SLAQG C0
Intel Core 2 Duo T9500 CPU SLAQH C0
Intel Core 2 Duo T9500 CPU SLAYY C0

19.2.9  Intel Core 2 Duo T8xxx series mobile processor (Penryn 3M)

Identification


Model name: Core 2 Duo T8xxx series.
Code name: Penryn 3M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 3 Mbyte.

Architecture


100-200 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Intel Dynamic Acceleration (IDA): while running extended serial code, one core can temporary run at a higher frequency while the other is turned off, so the total power dissipation stays within the operating limits.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
200/2100 MHz Intel Core 2 Duo T8100 CPU 10.5 January 2008 OEM (BGA): EC80576GG0453M,
OEM (PGA): FF80577GG0453M,
PIB (PGA): BX80577T8100
200/2400 MHz Intel Core 2 Duo T8300 CPU 12 January 2008 OEM (BGA): EC80577GG0563M,
OEM (BGA): EC80577GG0563MB,
OEM (PGA): FF80577GG0563M,
PIB (PGA): BX80577T8300

Physics


Voltage: (1.00-1.250 V).
Power dissipation: 35 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 45 nm (P1266).

Packaging: Socket P.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping M0

Step level


Text:

Step levels: M0.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Duo T8100 CPU SLAP9 M0
Intel Core 2 Duo T8300 CPU SLAPA M0
Intel Core 2 Duo T8300 CPU SLAPR M0
Intel Core 2 Duo T8100 CPU SLAPT M0
Intel Core 2 Duo T8100 CPU SLAYP M0
Intel Core 2 Duo T8300 CPU SLAYQ M0

19.3  Intel Core 2 Solo mobile processor


19.3.1  Intel Core 2 Solo ULV U2xxx series mobile processor (Merom-L ULV)

Identification


Model name: Core 2 Solo ULV U2xxx series.
Code name: Merom-L ULV.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


No dual-core technology (second core disabled).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
L2 cache: 1 Mbyte.

Architecture


133 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


No dual-core technology (second core disabled).

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
133/1066 MHz Intel Core 2 Solo ULV U2100 CPU 8 September 2007 OEM: LE80537UE0041M
133/1200 MHz Intel Core 2 Solo ULV U2200 CPU 9 September 2007 OEM: LE80537UE0091M

Physics


Voltage: (0.860-0.975 V).
Power dissipation: 5.5 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Packaging: FCBGA6.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x6 0x1 stepping A1

Step level


Text:

Step levels: A1.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Solo ULV U2200 CPU SLAGL A1
Intel Core 2 Solo ULV U2100 CPU SLAGM A1

19.4  Intel Pentium Dual-Core mobile processor


19.4.1  Intel Pentium Dual-Core T2xxx series mobile processor (Merom 2M)

Identification


Model name: Pentium Dual-Core Mobile T2xxx series.
Code name: Merom 2M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 1 Mbyte (other 1 Mbyte disfunctional/disabled).

Architecture


133 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
133/1466 MHz Intel Pentium Dual-Core Mobile T2310 CPU 11 Q4 2007 OEM: LF80537GE0201M
133/1600 MHz Intel Pentium Dual-Core Mobile T2330 CPU 12 Q4 2007 OEM: LF80537GE0251MN
133/1733 MHz Intel Pentium Dual-Core Mobile T2370 CPU 13 Q4 2007 OEM: LF80537GE0301M
133/1866 MHz Intel Pentium Dual-Core Mobile T2390 CPU 14 Q2 2008  

Physics


Voltage: 1.075-1.175 V.
Power dissipation: 35 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 167 million.

Die size: 111 mm2.

Packaging: Socket P.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xD stepping M0

Step level


Text:

Step levels: M0.

S-Spec / Stepping code


Model Code Stepping
Intel Pentium Dual-Core Mobile T2370 CPU SLA4J M0
Intel Pentium Dual-Core Mobile T2330 CPU SLA4K M0
Intel Pentium Dual-Core Mobile T2310 CPU SLAEC M0

19.5  Intel (Mobile) Celeron M processor


19.5.1  Intel (Mobile) Celeron M 5x0-fused series processor (Merom-1024)

Identification


Model name: (Mobile) Celeron M 5x0-fused series.
Code name: Merom-1024.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Single core (other core disfunctional/disabled).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 1 Mbyte (other 3 Mbyte disfunctional/disabled).

Architecture


133 MHz QDR bus.

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Single core (other core disfunctional/disabled).

Multiplier


Power management


Power management:

  • no Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
133/1600 MHz Intel Celeron M 520-fused CPU 12 January 2007 OEM: LF80537NE0251M,
PIB: BX80537520
133/1733 MHz Intel Celeron M 530-fused CPU 13 March 2007 OEM: LF80537NE0301M,
PIB: BX80537530

Physics


Voltage: 0.95-1.30 V.
Power dissipation: 30 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket M.

System management


No remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2

Step level


Text:

Step levels: B2.

S-Spec / Stepping code


Model Code Stepping
Intel Celeron M 520-fused CPU QVMC B2 ES
Intel Celeron M 520-fused CPU SL9WT B2

19.5.2  Intel (Mobile) Celeron M 5x0 series processor (Merom-L, Standard Voltage)

Identification


Model name: (Mobile) Celeron M 5x0 series.
Code name: Merom-L, Standard Voltage.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Single core.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 1 Mbyte.

Architecture


133 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Single core.

Multiplier


Power management


Power management:

  • no Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Voltage Power dissipation Packaging Introduction Order part numbers
133/1600 MHz Intel Celeron M 520 CPU 12 1.100-1.250 V 26 W TDP Socket M June 2007 OEM: LF80537NE0251M,
PIB: BX80537520
133/1733 MHz Intel Celeron M 530 CPU 13 1.125-1.255 V /
1.25 V
26 W TDP /
31 W TDP
Socket M March 2007 OEM: LF80537NE0301M,
PIB: BX80537NE0301M,
PIB: BX80537530,
OEM (embedded, PGA): LF80537NE0301M,
OEM (embedded, BGA): LE80537NE0301M
133/1733 MHz Intel Celeron M 530 CPU 13 1.100-1.250 V 27 W TDP Socket P September 2007 OEM: LF80537NE0301MN,
PIB: BX80537530SR,
PIB: BX80537530T
133/1866 MHz Intel Celeron M 540 CPU 14 1.100-1.250 V 27-31 W TDP Socket P July 2007 OEM: LF80537NE0361M,
PIB: BX80537540
133/2000 MHz Intel Celeron M 550 CPU 15 1.100-1.250 V /
1.25 V
27 W TDP /
31 W TDP
Socket P September 2007 OEM: LF80537NE0411M,
PIB: BX80537550,
OEM (embedded, PGA): LF80537NE0411M,
OEM (embedded, BGA): LE80537NE0411M
133/2133 MHz Intel Celeron M 560 CPU 16 1.100-1.250 V 31 W TDP Socket P December 2007 OEM: LF80537NE0461M,
PIB: BX80537560

Physics


Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

System management


No remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x6 0x1 stepping A1

Step level


Text:

Step levels: A1.

S-Spec / Stepping code


Model Code Stepping Description
Intel Celeron M 530 CPU QVTH ES Socket M, Micro-FCPGA
Intel Celeron M 530 CPU QVGX A1 ES Socket M, Micro-FCPGA
Intel Celeron M 530 CPU SL9VA A1 1.125-1.255 V, 26 W TDP, Socket M, Micro-FCPGA
Intel Celeron M 520 CPU SL9WN A1 1.100-1.250 V, 26 W TDP, Socket M, Micro-FCPGA
Intel Celeron M 560 CPU SLA2D A1 1.100-1.250 V, 31 W TDP, Socket P, Micro-FCPGA
Intel Celeron M 550 CPU SLA2E A1 1.100-1.250 V, 27 W TDP, Socket P, Micro-FCPGA
Intel Celeron M 540 CPU SLA2F A1 1.100-1.250 V, 27-31 W TDP, Socket P, Micro-FCPGA
Intel Celeron M 530 CPU SLA2G A1 1.100-1.250 V, 27 W TDP, Socket P, Micro-FCPGA

19.5.3  Intel (Mobile) Celeron M ULV 5x3 series processor (Merom-L, Ultra Low Voltage)

Identification


Model name: (Mobile) Celeron M ULV 5x3 series.
Code name: Merom-L, Ultra Low Voltage.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Single core.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 1 Mbyte.

Architecture


133 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Single core.

Multiplier


Power management


Power management:

  • no Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Packaging Introduction
133/933 MHz Intel Celeron M 523 ULV CPU 7 FCBGA6 September 2007

Physics


Power dissipation: 5 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket M.

System management


No remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x6 0x1 stepping A1

Step level


Text:

Step levels: A1.

19.6  Intel Core 2 Extreme mobile processor


19.6.1  Intel Core 2 Extreme X7xxx series mobile processor (Merom XE)

Identification


Model name: Core 2 Extreme X7xxx series.
Code name: Merom XE.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


100-200 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Unlocked clock multiplier.

Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
200/2600 MHz Intel Core 2 Extreme X7800 CPU 13 (unlocked) July 2007 OEM: LF80537GG0644M
200/2800 MHz Intel Core 2 Extreme X7900 CPU 14 (unlocked) July 2007 OEM: LF80537GG0724M

Physics


Voltage:

  • stepping E1: 1.10-1.375 V (1.0375-1.30 V),
  • stepping G0: 1.125-1.325 V (1.0375-1.30 V).

Power dissipation: 34 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket P.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xA stepping E1
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels: E1, G0.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Duo X7900 CPU SLA33 E1
Intel Core 2 Duo X7800 CPU SLA6Z E1
Intel Core 2 Duo X7900 CPU SLAF4 G0

19.6.2  Intel Core 2 Extreme X9xxx series mobile processor (Penryn XE)

Identification


Model name: Core 2 Duo X9xxx series.
Code name: Penryn XE.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 6 Mbyte.

Architecture


100-266 MHz QDR bus (Dynamic Front-Side Bus Frequency Switching).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Intel Dynamic Acceleration (IDA): while running extended serial code, one core can temporary run at a higher frequency while the other is turned off, so the total power dissipation stays within the operating limits.

Multiplier


Unlocked clock multiplier.

Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
200/2800 MHz Intel Core 2 Extreme X9000 CPU 14 (unlocked) January 2008 OEM: FF80576ZG0726M
266/2066 MHz Intel Core 2 Extreme X9100 CPU 11.5 (unlocked) April 2008  

Physics


Voltage: (1.062-1.150 V).
Power dissipation: 44 W TDP.

Temperature: 0-100 °C.

Manufacturing process: 45 nm (P1266).

Number of transistors: 410 million.

Die size: 110 mm2.

Packaging: Socket P.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping M0

Step level


Text:

Step levels: M0.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Extreme X9000 CPU SLAQJ M0
Intel Core 2 Extreme X9000 CPU SLAZ3 M0

19.7  Intel Pentium Dual-Core processor


19.7.1  Intel Pentium Dual-Core E2xxx series processor (Allendale)

Identification


Model name: Pentium Dual-Core E2xxx series.
Code name: Allendale.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 1 Mbyte (other 1 Mbyte disfunctional/disabled).

Architecture


200 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E): 8 W,
  • Extended Stop Grant State (C2E).

Clock speed


Clock speed Model Multiplier Temperature Introduction Marking Order part numbers
200/1600 MHz Intel Pentium Dual-Core E2140 CPU 8   June 2007 PCG: 06 OEM (stepping L2, M0): HH80557PG0251M,
PIB (stepping L2, M0): BX80557E2140,
PIB (stepping L2, M0): BXC80557E2140
200/1800 MHz Intel Pentium Dual-Core E2160 CPU 9   June 2007 PCG: 06 OEM (stepping L2, M0): HH80557PG0331M,
PIB (stepping L2, M0): BX80557E2160,
PIB (stepping L2, M0): BXC80557E2160
200/2000 MHz Intel Pentium Dual-Core E2180 CPU 10   August 2007 PCG: 06 OEM (stepping M0): HH80557PG0411M,
PIB (stepping M0): BX80557E2180
200/2200 MHz Intel Pentium Dual-Core E2200 1 CPU 11 5-73.3 °C December 2007 PCG: 06 OEM (stepping M0): HH80557PG0491M,
PIB (stepping M0): BX80557E2200
200/2400 MHz Intel Pentium Dual-Core E2220 CPU 12 5-73.3 °C March 2008 PCG: 06 OEM (stepping M0): HH80557PG0561M,
PIB (stepping M0): BXC80557E2220,
PIB (stepping M0): BX80557E2220

  1. voltage: 1.162-1.312 V

Physics


Voltage: 0.85-1.50 V.
Power dissipation: 65 W TDP.

Temperature:

  • stepping L2: 5-61.4 °C,
  • stepping M0: 5-73.2 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 167 million.

Die size: 111 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x2 stepping L2
0x0 0x6 0xF 0xD stepping M0

Step level


Text:

Step levels:

  • L2,
  • M0 (July 22, 2007).

S-Spec / Stepping code


Model Code Stepping Description Introduction
Intel Pentium Dual-Core E2160 CPU SLA3H L2    
Intel Pentium Dual-Core E2140 CPU QYGD ES    
Intel Pentium Dual-Core E2140 CPU SLA3J L2    
Intel Pentium Dual-Core E2220 CPU SLA8W M0    
Intel Pentium Dual-Core E2200 CPU SLA8X M0 C2E  
Intel Pentium Dual-Core E2180 CPU SLA8Y M0 C2E  
Intel Pentium Dual-Core E2160 CPU SLA8Z M0    
Intel Pentium Dual-Core E2140 CPU QYRG M0 QS   July 2007
Model Code Stepping Description Introduction
Intel Pentium Dual-Core E2140 CPU SLA93 M0 C2E  

19.8  Intel Celeron processor


19.8.1  Intel Celeron 400/200 series processor (Conroe-L, Merom-Chop2)

Identification


Model name: Celeron 400/200 series.
Code name: Conroe-L (Merom-Chop2).
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Single core.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
L2 cache: 512 kbyte.

Architecture


200/133 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Single core.

Multiplier


Power management


Power management:

  • no Enhanced Intel SpeedStep Technology (EIST),
  • Halt state (C1), Stop-Grant state,
  • Celeron 420 and 220 only: Enhanced Halt state (C1E):
    • Celeron 420: 8 W.

Clock speed


Clock speed Model Multiplier Packaging Introduction Cancellation Order part numbers
133/1200 MHz Intel Celeron 220 1 CPU 9 FCBGA6 October 2007 May 2009 OEM: LE80557RE009512
200/1600 MHz Intel Celeron 420 CPU 8   June 2007   OEM: HH80557RG025512,
PIB: BX80557420,
PIB: BXC80557420
200/1800 MHz Intel Celeron 430 CPU 9   June 2007   OEM: HH80557RG033512,
PIB: BX80557430,
PIB: BXC80557430
200/2000 MHz Intel Celeron 440 CPU 10   June 2007   OEM: HH80557RG041512,
PIB: BX80557440,
PIB: BXC80557440

  1. Intel Desktop Boards Essential Series: soldered on D201GLY2 motherboard, passively cooled

Physics


Voltage: 1.05-1.30 V (1.0000-1.3375 V).
Power dissipation:

  • Celeron 220: 19 W TDP,
  • others: 35 W TDP.

Temperature:

  • Celeron 220: 0-100 °C,
  • others: 5-60.4 °C.

Manufacturing process: 65 nm (P1264).

Packaging: Socket T / LGA 775.

Thermal management


Thermal management:

  • TM2 (Thermal Monitor),
  • Celeron 420 and 220 only: thermal diode (Tdiode),
  • Platform Environment Control Interface (PECI).

System management


No remote management.

Marking


Platform Compatibility Guide (PCG): 06.

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x6 0x1 stepping A1

Step level


Text:

Step levels: A1.

S-Spec / Stepping code


Model Code Stepping
Intel Celeron 440 CPU SL9XL A1
Intel Celeron 430 CPU SL9XN A1
Intel Celeron 420 CPU SL9XP A1
Intel Celeron 220 CPU SLAF2 A1

19.8.2  Intel Celeron E1xxx series Dual-Core processor (Allendale-512)

Identification


Model name: Celeron E1xxx series Dual-Core.
Code name: Allendale-512.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 512 kbyte.

Architecture


200 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

No protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

No Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Halt state (C1), Stop-Grant state,
  • Enhanced Halt state (C1E).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
200/1600 MHz Intel Celeron E1200 Dual-Core CPU 8 January 2008 OEM: HH80557PG025D,
PIB: BX80557E1200,
PIB: BXC80557E1200F
200/2000 MHz Intel Celeron E1400 Dual-Core CPU 10 April 2008 OEM: HH80557PG041D,
PIB: BX80557E1400,
PIB: BXC80557E1400

Physics


Voltage: 1.162-1.312 V.
Power dissipation: 65 W TDP.

Temperature: 5-73.3 °C.

Manufacturing process: 65 nm (P1264).

Packaging: Socket T / LGA 775.

Thermal management


Thermal management:

  • TM2 (Thermal Monitor).

System management


No remote management.

Marking


Platform Compatibility Guide (PCG): 06.

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xD stepping M0

Step level


Text:

Step levels: M0.

S-Spec / Stepping code


Model Code Stepping
Intel Celeron E1200 Dual-Core CPU SLAQW M0
Intel Celeron E1400 Dual-Core CPU SLAR2 M0

19.9  Intel Core 2 Extreme processor


19.9.1  Intel Core 2 Extreme X6xxx series processor (Conroe XE)

Identification


Model name: Core 2 Extreme X6xxx series.
Code name: Conroe XE.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

Multiplier


Unlocked clock multiplier.

Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/2933 MHz Intel Core 2 Extreme X6800 CPU 11 (unlocked) July 2006 OEM: HH80557PH0677M,
PIB: BX80557X6800

Physics


Voltage: 0.85-1.3525 V.
Power dissipation: 75 W TDP.

Temperature: max. 60.4 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2

Step level


Text:

Step levels: B2.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Extreme X6800 CPU SL9S5 B2 PCG: 05B

19.10  Intel Core 2 Dual-Core Xeon processor


19.10.1  Intel Core 2 Dual-Core Xeon DP 51xx series processor (Woodcrest)

Identification


Model name: Core 2 Dual-Core Xeon DP 51xx series.
Code name: Woodcrest.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


266/333 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Symmetric Multi-Processing (SMP): max. 2-way.

Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Power dissipation Introduction Order part numbers
266/1600 MHz Intel Core 2 Dual-Core Xeon DP 5110 1 CPU 6 65 W TDP June 2006 OEM: HH80556KH0254M,
PIB (active): BX805565110A,
PIB (passive): BX805565110P
266/1866 MHz Intel Core 2 Dual-Core Xeon DP 5120 1 CPU 7 65 W TDP June 2006 OEM: HH80556KH0364M,
PIB (active): BX805565120A,
PIB (passive): BX805565120P
333/2000 MHz Intel Core 2 Dual-Core Xeon DP 5130 1 CPU 6 65 W TDP June 2006 OEM: HH80556KJ0414M,
PIB (active): BX805565130A,
PIB (passive): BX805565130P
333/2333 MHz Intel Core 2 Dual-Core Xeon DP 5140 CPU 7 65 W TDP June 2006 OEM: HH80556KJ0534M,
PIB (active): BX805565140A,
PIB (passive): BX805565140P
333/2666 MHz Intel Core 2 Dual-Core Xeon DP 5150 CPU 8 65 W TDP June 2006 OEM: HH80556KJ0674M,
PIB (active): BX805565150A,
PIB (passive): BX805565150P
333/3000 MHz Intel Core 2 Dual-Core Xeon DP 5160 CPU 9 80 W TDP June 2006 OEM: HH80556KJ0804M,
PIB (active): BX805565160A,
PIB (passive): BX805565160P

  1. no Enhanced Intel SpeedStep Technology (EIST)

Physics


Voltage: 1.0-1.5 V.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket J / LGA 771.

19.10.2  Intel Core 2 Dual-Core Xeon DP LV 51xx series processor (Woodcrest LV)

Identification


Model name: Core 2 Dual-Core Xeon DP LV 51xx series.
Code name: Woodcrest LV.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


266/333 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Symmetric Multi-Processing (SMP): max. 2-way.

Dual-core technology.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Voltage Power dissipation Introduction Order part numbers
266/1866 MHz Intel Core 2 Dual-Core Xeon DP LV 5128 CPU 7 1.15-1.25 V 40 W TDP Q4 2006 OEM: HH80556JH0364M
266/2133 MHz Intel Core 2 Dual-Core Xeon DP LV 5138 CPU 8   35 W TDP Q4 2006 OEM: HH80556JH0464M
333/2333 MHz Intel Core 2 Dual-Core Xeon DP LV 5138 CPU 7 1.15-1.25 V 40 W TDP Q3 2006 OEM: HH80556JJ0534M,
PIB (active): BX805565148A,
PIB (passive): BX805565148P

Physics


Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket J / LGA 771.

19.10.3  Intel Core 2 Dual-Core Xeon UP 30xx series processor (Conroe)

Identification


Model name: Core 2 Dual-Core Xeon UP 30xx series.
Code name: Conroe.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

SMP (Symmetric Multi-Processing) not supported.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/2400 MHz Intel Core 2 Dual-Core Xeon UP LV 3060 CPU 9 October 2006 OEM: HH80557KH0564M,
PIB: BX805573060
266/2667 MHz Intel Core 2 Dual-Core Xeon UP LV 3070 CPU 10 October 2006 OEM: HH80557KH0674M,
PIB: BX805573070

Physics


Voltage: 0.85-1.5 V.
Power dissipation: 65 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket T / LGA 775.

System management


No remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2

Step level


Text:

Step levels: B2.

S-Spec / Stepping code


Model Code Stepping Description Introduction
Intel Core 2 Dual-Core Xeon UP LV 3060 CPU SL9TZ B2    
Intel Core 2 Dual-Core Xeon UP LV 3070 CPU SL9U2 B2    
Intel Core 2 Dual-Core Xeon UP LV 3070 CPU SL9ZC B2 Extended HALT power specification reduced from 20-22 W to 12 W December 2006
Intel Core 2 Dual-Core Xeon UP LV 3060 CPU SL9ZH B2 Extended HALT power specification reduced from 20-22 W to 12 W December 2006

19.10.4  Intel Core 2 Dual-Core Xeon UP 30xx series processor (Conroe 2M)

Identification


Model name: Core 2 Dual-Core Xeon UP 30xx series.
Code name: Conroe 2M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Dual-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Shared L2 cache: 2 Mbyte (other 2 Mbyte disfunctional/disabled).

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Dual-core technology.

SMP (Symmetric Multi-Processing) not supported.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/1866 MHz Intel Core 2 Dual-Core Xeon UP LV 3040 CPU 7 October 2006 OEM: HH80557KH0362M,
PIB: BX805573040
266/2133 MHz Intel Core 2 Dual-Core Xeon UP LV 3050 CPU 8 October 2006 OEM: HH80557KH0462M,
PIB: BX805573050

Physics


Voltage: 0.85-1.5 V.
Power dissipation: 65 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: 291 million.

Die size: 143 mm2.

Packaging: Socket T / LGA 775.

System management


No remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x6 stepping B2
0x0 0x6 0xF 0x2 stepping L2

Step level


Text:

Step levels:

  • B2,
  • L2 (December 15, 2006): Extended HALT power specification reduced from 22 W to 12 W.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Dual-Core Xeon UP LV 3040 CPU SL9TW B2
Intel Core 2 Dual-Core Xeon UP LV 3050 CPU SL9TY B2
Intel Core 2 Dual-Core Xeon UP LV 3050 CPU QUUG L2 QS
Intel Core 2 Dual-Core Xeon UP LV 3050 CPU SL9VS L2
Intel Core 2 Dual-Core Xeon UP LV 3040 CPU QUUK L2 QS
Intel Core 2 Dual-Core Xeon UP LV 3040 CPU SL9VT L2

19.11  Intel Core 2 Quad processor


19.11.1  Intel Core 2 Quad Q6xxx series processor (Kentsfield)

Identification


Model name: Core 2 Quad Q6xxx series.
Code name: Kentsfield.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/2400 MHz Intel Core 2 Quad Q6600 CPU 9 January 2007 OEM (stepping B3, G0): HH80562PH0568M,
PIB (stepping B3, G0): BX80562Q6600
266/2667 MHz Intel Core 2 Quad Q6700 CPU 10 July 2007 OEM (stepping G0): HH80562PH0678MK,
PIB (stepping G0): BX80562Q6700

Physics


Voltage: 1.10-1.372 V (0.85-1.50 V).
Power dissipation:

  • step level B3: 105 W TDP,
  • step level G0: 95 W TDP.

Temperature:

  • step level B3: 62.2 °C,
  • step level G0: 71 °C.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x7 stepping B3
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels:

  • B3: 105 W TDP; thermal specification: 62.2 °C,
  • G0 (July 27, 2007): 95 W TDP; thermal specification: 73.2 °C.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Quad Extreme Q6600 CPU SL9UM B3 PCG: 05B
Intel Core 2 Quad Extreme Q6600 CPU SLACR G0 PCG: 05A
Intel Core 2 Quad Extreme Q6700 CPU SLACQ G0 PCG: 05A

19.11.2  Intel Core 2 Quad Q9xxx series processor (Yorkfield)

Identification


Model name: Core 2 Quad Q9xxx series.
Code name: Yorkfield.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3. SSSE3, SSE4.1.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 6 Mbyte, 12-way set-associative.

Architecture


333 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E),
  • Extended Stop Grant State (C2E),
  • Deep Sleep State (C3E),
  • Deeper Sleep State (C4E),
  • from stepping E0: ACNT2,
  • from stepping E0: Power Status Indicator (PSI).

Clock speed


Clock speed Model Multiplier Power dissipation Introduction Marking Order part numbers
333/2666 MHz Intel Core 2 Quad Q9450 CPU 8 95 W TDP March 2008 PCG: 05A OEM (stepping C0, C1): EU80569PJ067N,
PIB: BX80569Q9450,
PIB (for China): BXC80569Q9450
333/2833 MHz Intel Core 2 Quad Q9550 CPU 8.5 95 W TDP March 2008 PCG: 05A OEM (stepping C0, C1): EU80569PJ073N,
OEM (stepping E0, halide-free): AT80569PJ073N,
PIB: BX80569Q9550,
PIB (for China): BXC80569Q9550
333/2833 MHz Intel Core 2 Quad Q9550S CPU 8.5 65 W TDP January 2009 PCG: 06 OEM (stepping E0, halide-free): AT80569AJ073N,
PIB: BX80569Q9550S
333/3000 MHz Intel Core 2 Quad Q9650 CPU 9 95 W TDP August 2008 PCG: 05A OEM (stepping E0, halide-free): AT80569PJ080N,
PIB: BX80569Q9650,
PIB (for China): BXC80569Q9650

Physics


Voltage: 0.8500-1.3625 V.
Power dissipation: 95 W TDP.

Temperature:

  • 95 W TDP: 5-71.4 °C,
  • 65 W TDP: 5-76.3 °C.

Manufacturing process: 45 nm (P1266).

Number of transistors: (2x) 410 million.

Die size: (2x) 107 mm2.

Packaging: Socket T / LGA 775.

Thermal management


Thermal management:

  • Platform Environment Control Interface (PECI),
  • PROCHOT# (Thermal Control Circuit, TCC),
  • THERMTRIP#.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping C0
0x0 0x1 0x0 0x6 0x7 0x7 stepping C1
0x0 0x1 0x0 0x6 0x7 0xA stepping E0

Step level


Text:

Step levels:

  • C0,
  • C1,
  • E0 (July 7, 2008):
    • Power Status Indicator (PSI),
    • PECI implementation change,
    • XSAVE/XRSTOR instructions,
    • ACNT2 processor utilization determination,
    • Halide free package.

S-Spec / Stepping code


Model Code Stepping Description Introduction
Intel Core 2 Quad Q9550 CPU Q5MV ES    
Intel Core 2 Quad Q9550 CPU Q9PT C0 ES    
Intel Core 2 Quad Q9550 CPU SLAN4 C0 no C2E, C3E, C4E  
Intel Core 2 Quad Q9450 CPU Q7UP C0 sample    
Intel Core 2 Quad Q9450 CPU SLAN6 C0 no C2E, C3E, C4E  
Intel Core 2 Quad Q9450 CPU SLAWN C1 no C2E, C3E, C4E  
Intel Core 2 Quad Q9550 CPU SLAWQ C1 no C2E, C3E, C4E  
Intel Core 2 Quad Q9450 CPU SLAWR C1 no C2E, C3E, C4E  
Model Code Stepping Description Introduction
Intel Core 2 Quad Q9550 CPU QGPK E0 QS   May 2008
Intel Core 2 Quad Q9550 CPU SLB8V E0 no C2E August 2008
Intel Core 2 Quad Q9650 CPU QHGF E0 sample    
Intel Core 2 Quad Q9650 CPU SLB8W E0    
Intel Core 2 Quad Q9550S CPU QJMG E0 ES    
Intel Core 2 Quad Q9550S CPU SLGAE E0 no C2E  

19.11.3  Intel Core 2 Quad Q9xxx/Q8xxx series processor (Yorkfield-6M)

Identification


Model name: Core 2 Quad Q9xxx/Q8xxx series.
Code name: Yorkfield-6M.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3. SSSE3, SSE4.1.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 3 Mbyte, 12-way set-associative.

Architecture


333 MHz QDR Front-Side Bus (FSB).

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Multiplier


Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E),
  • Extended Stop Grant State (C2E),
  • Deep Sleep State (C3E),
  • Deeper Sleep State (C4E),
  • from stepping E0: ACNT2,
  • from stepping E0: Power Status Indicator (PSI).

Clock speed


Clock speed Model Multiplier Power dissipation Introduction Marking Order part numbers
333/2500 MHz Intel Core 2 Quad Q9300 CPU 7.5 95 W TDP March 2008 PCG: 05A OEM (stepping M0, M1): EU80580PJ0606M,
PIB: BX80580Q9300,
PIB (for China): BXC80580Q9300
333/2667 MHz Intel Core 2 Quad Q9400 CPU 8 95 W TDP August 2008 PCG: 05A OEM (stepping R0, halide-free): AT80580PJ0676M,
PIB: BX80580Q9400,
PIB (for China): BXC80580Q9400
333/2667 MHz Intel Core 2 Quad Q9400S CPU 8 65 W TDP January 2009 PCG: 06 OEM (stepping R0, halide-free): AT80580AJ0676M,
PIB: BX80580Q9400S

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 2 Mbyte (other (2x) 1 Mbyte disfunctional/disabled), 12-way set-associative.

Clock speed


Clock speed Model Multiplier Power dissipation Introduction Marking Order part numbers
333/2333 MHz Intel Core 2 Quad Q8200 CPU 7 95 W TDP August 2008 PCG: 05A OEM (stepping M1): EU80580PJ0534MN,
OEM (stepping R0, halide-free): AT80580PJ0534MN,
PIB: BX80580Q8200,
PIB (for China): BXC80580Q8200
333/2333 MHz Intel Core 2 Quad Q8200S CPU 7 65 W TDP January 2009 PCG: 06 OEM (stepping R0, halide-free): AT80580AJ0534MN,
PIB: BX80580Q8200S
333/2500 MHz Intel Core 2 Quad Q8300 CPU 7.5 95 W TDP November 2008 PCG: 05A OEM (stepping R0, halide-free): AT80580PJ0604MN,
PIB: BX80580Q8300,
PIB (for China): BXC80580Q8300

Physics


Voltage: 0.8500-1.3625 V (0.962-1.225 V).
Power dissipation: 95/65 W TDP.

Temperature:

  • 95 W TDP: 5-71.4 °C,
  • 65 W TDP: 5-76.3 °C.

Manufacturing process: 45 nm (P1266).

Die size: (2x) 82 mm2.

Packaging: Socket T / LGA 775.

Thermal management


Thermal management:

  • Platform Environment Control Interface (PECI),
  • PROCHOT# (Thermal Control Circuit, TCC),
  • THERMTRIP#.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
    0x0 0x6 0x7 0x4 stepping B1
0x0 0x1 0x0 0x6 0x7 0x6 stepping M0
0x0 0x1 0x0 0x6 0x7 0x7 stepping M1
0x0 0x1 0x0 0x6 0x7 0xA stepping R0

Step level


Text:

Step levels:

  • B1,
  • M0,
  • M1,
  • R0.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Quad Q9300 CPU QAKY B1 ES  
Intel Core 2 Quad Q9300 CPU SLAMX M0 no C2E, C3E, C4E
Intel Core 2 Quad Q9300 CPU SLAWE M1 no C2E, C3E, C4E
Intel Core 2 Quad Q8200 CPU SLB5M M1 no C2E, C3E, C4E
Intel Core 2 Quad Q8300 CPU QHJC R0 sample  
Intel Core 2 Quad Q8300 CPU SLB5W R0  
Intel Core 2 Quad Q9400 CPU QHHU R0 ES  
Intel Core 2 Quad Q9400 CPU SLB6B R0  
Model Code Stepping Description
Intel Core 2 Quad Q8200 CPU SLG9S R0 no C2E
Intel Core 2 Quad Q8200S CPU SLG9T R0 no C2E
Intel Core 2 Quad Q9400S CPU SLG9U R0 no C2E

19.12  Intel Core 2 Quad Extreme processor


19.12.1  Intel Core 2 Quad Extreme QX6xxx series processor (Kentsfield XE)

Identification


Model name: Core 2 Quad Extreme QX6xxx series.
Code name: Kentsfield XE.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Multiplier


Unlocked clock multiplier (x6 - x16).

Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E).

Clock speed


Clock speed Model Multiplier Temperature Introduction Cancellation Order part numbers
266/2667 MHz Intel Core 2 Quad Extreme QX6700 CPU 10 (unlocked) max. 65 °C November 2006   OEM (stepping B3): HH80562PH0678M,
PIB (stepping B3): BX80562QX6700
266/2933 MHz Intel Core 2 Quad Extreme QX6800 CPU 11 (unlocked) stepping B3: 5-54.8 °C,
stepping G0: max. 64.5 °C
April 2007 May 2009 OEM (stepping B3, G0): HH80562PH0778M,
OEM (stepping G0): HH80562XH0778M,
PIB (stepping B3, G0): BX80562PH0778M,
PIB (stepping G0): BX80562QX6800
333/3000 MHz Intel Core 2 Quad Extreme QX6850 CPU 9 (unlocked) max. 64.5 °C July 2007 May 2009 OEM (stepping G0): HH80562XJ0808M,
PIB (stepping G0): BX80562QX6850

Physics


Voltage: 1.100-1.372 V (0.85-1.50 V).
Power dissipation: 130 W TDP

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x7 stepping B3
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels:

  • B3: Extended HALT power (C1E): 50 W, thermal specification: 54.8/65 °C,
  • G0 (July 27, 2007): Extended HALT power (C1E): 37 W, thermal specification: 64.5 °C.

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Quad Extreme QX6700 CPU SL9UL B3 PCG: 05B
Intel Core 2 Quad Extreme QX6800 CPU SL9UK B3  
Intel Core 2 Quad Extreme QX6800 CPU SLACP G0 PCG: 05B
Intel Core 2 Quad Extreme QX6850 CPU SLAFN G0 PCG: 05B

19.12.2  Intel Core 2 Quad Extreme QX9xxx series processor (Yorkfield XE)

Identification


Model name: Core 2 Quad Extreme QX9xxx series.
Code name: Yorkfield XE.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology.

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3. SSSE3, SSE4.1.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 6 Mbyte.

Architecture


333/400 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

QX9775: Intel I/O Acceleration Technology (I/OAT).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Multiplier


Unlocked clock multiplier (x6 - x16).

Power management


Power management:

  • Enhanced Intel SpeedStep Technology (EIST),
  • Enhanced Halt State (C1E).

Clock speed


Clock speed Model Multiplier Voltage Power dissipation Temperature Packaging Introduction Order part numbers
333/3000 MHz Intel Core 2 Quad Extreme QX9650 CPU 9 (unlocked) 0.8500-1.3625 V 130 W TDP max. 64.5 °C Socket T / LGA 775 November 2007 OEM: EU80569XJ080NL,
PIB: BX80569QX9650
400/3200 MHz Intel Core 2 Quad Extreme QX9770 CPU 8 (unlocked) 0.8500-1.3625 V 136 W TDP max. 55.5 °C Socket T / LGA 775 Q1 2008 OEM: EU80569XL088NL,
PIB: BXC80569QX9770,
PIB: BX80569QX9770
400/3200 MHz Intel Core 2 Quad Extreme QX9775 1 CPU 8 (unlocked) 1.212 V 150 W TDP max. 63.0 °C Socket J / LGA 771 Q1 2008 OEM: EU80574XL088N,
PIB: BX80574QX9775

  1. Intel I/O Acceleration Technology (I/OAT)

Physics


Manufacturing process: 45 nm (P1266).

Number of transistors: (2x) 410 million.

Die size: (2x) 107 mm2.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Extended family Extended model Type Family Model Stepping Description
0x0 0x1 0x0 0x6 0x7 0x6 stepping C0
0x0 0x1 0x0 0x6 0x7 0x7 stepping C1

Step level


Text:

Step levels:

  • C0: Extended HALT power (C1E): 16 W,
  • C1 (March 8, 2008).

S-Spec / Stepping code


Model Code Stepping Description
Intel Core 2 Quad Extreme QX9770 CPU SLAN2 C0  
Intel Core 2 Quad Extreme QX9650 CPU SLAN3 C0 PCG: 05B
Intel Core 2 Quad Extreme QX9775 CPU SLANY C0  
Intel Core 2 Quad Extreme QX9770 CPU SLAWM C1 PCG: 05B
Intel Core 2 Quad Extreme QX9650 CPU SLAWN C1 PCG: 05B

19.13  Intel Core 2 Quad Xeon processor


19.13.1  Intel Core 2 Quad Xeon DP E53xx/X53xx series processor (Cloverton)

Identification


Model name: Core 2 Quad Xeon DP E53xx/X53xx series.
Code name: Cloverton.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte.

Architecture


266/333 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Symmetric Multi-Processing (SMP): max. 2-way.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Voltage Power dissipation Introduction Order part numbers
266/1600 MHz Intel Core 2 Quad-Core Xeon DP E5310 CPU 6 1.0-1.5 V 80 W TDP November 2006 OEM: HH80563QH0258M,
PIB (active): BX80563E5310A,
PIB (passive): BX80563E5310P
266/1866 MHz Intel Core 2 Quad-Core Xeon DP E5320 CPU 7 1.0-1.5 V 80 W TDP November 2006 OEM: HH80563QH0368M,
PIB (active): BX80563E5320A,
PIB (passive): BX80563E5320P
333/2000 MHz Intel Core 2 Quad-Core Xeon DP E5335 CPU 6 1.0-1.5 V 80 W TDP December 2006 OEM: HH80563QJ0418M
333/2333 MHz Intel Core 2 Quad-Core Xeon DP E5345 CPU 7 1.162-1.200 V 80 W TDP November 2006 OEM: HH80563QJ0538M,
PIB (active): BX80563E5345A,
PIB (passive): BX80563E5345P
333/2667 MHz Intel Core 2 Quad-Core Xeon DP X5355 CPU 8 1.162-1.200 V 120 W TDP November 2006 OEM: HH80563KJ0678M,
PIB (active): BX80563X5355A,
PIB (passive): BX80563X5355P
333/3000 MHz Intel Core 2 Quad-Core Xeon DP X5365 CPU 9   120 W TDP August 2007  

Physics


Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket J / LGA 771.

System management


Remote management: Intel Active Management (iAMT2).

Step level


Text:

Step levels: B3.

19.13.2  Intel Core 2 Quad Xeon DP LV L53xx series processor (Cloverton LV)

Identification


Model name: Core 2 Quad Xeon DP LV L53xx series.
Code name: Cloverton LV.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Symmetric Multi-Processing (SMP): max. 2-way.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction
266/1600 MHz Intel Core 2 Quad-Core Xeon DP LV L5310 CPU 6 March 2007
266/1866 MHz Intel Core 2 Quad-Core Xeon DP LV L5320 CPU 7 March 2007
333/2000 MHz Intel Core 2 Quad-Core Xeon DP LV L5335 CPU 6 August 2007

Physics


Power dissipation: 50 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket J / LGA 771.

System management


Remote management: Intel Active Management (iAMT2).

Step level


Text:

Step levels: B3.

19.13.3  Intel Core 2 Quad Xeon UP X32xx series processor (Kentsfield)

Identification


Model name: Core 2 Quad Xeon UP X32xx series.
Code name: Kentsfield.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte.

Architecture


266 MHz QDR bus.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool).

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

No Symmetric Multi-Processing (SMP).

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/2133 MHz Intel Core 2 Quad-Core Xeon UP X3210 CPU 8 January 2007 OEM: HH80562QH0468M
266/2400 MHz Intel Core 2 Quad-Core Xeon UP X3220 CPU 9 January 2007 OEM: HH80562QH0568M

Physics


Voltage: 1.100-1.372 V.
Power dissipation:

  • step level B3: 105 W TDP,
  • step level G0: 95 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket T / LGA 775.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0x7 stepping B3
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels:

  • B3: 105 W TDP; thermal specification: 62.2 °C,
  • G0 (July 27, 2007): 95 W TDP; thermal specification: 73.2 °C.

S-Spec / Stepping code


Model Code Stepping
Intel Core 2 Quad-Core Xeon UP X3220 CPU SL9UP B3
Intel Core 2 Quad-Core Xeon UP X3210 CPU SL9UQ B3
Intel Core 2 Quad-Core Xeon UP X3220 CPU SLACT G0
Intel Core 2 Quad-Core Xeon UP X3210 CPU SLACU G0

19.13.4  Intel Quad-Core Xeon MP E7300/X7300 series processor (Tigerton)

Identification


Model name: Quad-Core Xeon MP E7300/X7300 series.
Code name: Tigerton.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 2/3/4 Mbyte.

Architecture


266 MHz QDR Dedicated High Speed Interconnect (DHSI): connecting the CPU socket directly to the chipset on the motherboard (Multi Independent Bus, MIB); main memory talks to the chipset, not directly to the processor chips.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool), with:

  • VT FlexMigration: enabling future processor generations to impersonate a previous generation, allowing virtual machines (vms) to live migrate to another processor generation without disturbing the architectural image that applications are having.

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Symmetric Multi-Processing (SMP): supported through chipset.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Cache Multiplier Introduction Order part numbers
266/1600 MHz Intel Quad-Core Xeon MP E7310 1 CPU (2x) 2 Mbyte L2 6 September 2007 OEM: LF80565QH0254M
266/2133 MHz Intel Quad-Core Xeon MP E7320 CPU (2x) 2 Mbyte L2 8 September 2007 OEM: LF80565QH0464M
266/2400 MHz Intel Quad-Core Xeon MP E7330 CPU (2x) 3 Mbyte L2 9 September 2007 OEM: LF80565QH0566M
266/2400 MHz Intel Quad-Core Xeon MP E7340 CPU (2x) 4 Mbyte L2 9 September 2007 OEM: LF80565QH0568M
266/2933 MHz Intel Quad-Core Xeon MP X7350 CPU (2x) 4 Mbyte L2 11 September 2007 OEM: LF80565KH0778M

  1. no EIST

Physics


Voltage: 1.20-1.35 V.
Power dissipation:

  • E7300 series: 80 W TDP,
  • X7300 series: 130 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket 604.

Thermal management


Thermal Monitor: TM1, TM2.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels: G0.

S-Spec / Stepping code


Model Code Stepping
Intel Quad-Core Xeon MP X7350 CPU SLA67 G0
Intel Quad-Core Xeon MP E7340 CPU SLA68 G0
Intel Quad-Core Xeon MP E7320 CPU SLA69 G0
Intel Quad-Core Xeon MP E7310 CPU SLA6A G0
Intel Quad-Core Xeon MP E7330 CPU SLA77 G0

19.13.5  Intel Quad-Core Xeon MP LV L7300 series processor (Tigerton LV)

Identification


Model name: Quad-Core Xeon MP LV L7300 series.
Code name: Tigerton LV.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (4x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte.

Architecture


266 MHz QDR Dedicated High Speed Interconnect (DHSI): connecting the CPU socket directly to the chipset on the motherboard (Multi Independent Bus, MIB); main memory talks to the chipset, not directly to the processor chips.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool), with:

  • VT FlexMigration: enabling future processor generations to impersonate a previous generation, allowing virtual machines (vms) to live migrate to another processor generation without disturbing the architectural image that applications are having.

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).

Symmetric Multi-Processing (SMP): supported through chipset.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/1866 MHz Intel Quad-Core Xeon MP LV L7345 CPU 7 September 2007 OEM: LF80565JH0368M

Physics


Voltage: 1.10-1.25 V.
Power dissipation: 50 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket 604.

Thermal management


Thermal Monitor: TM1, TM2.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels: G0.

S-Spec / Stepping code


Model Code Stepping
Intel Quad-Core Xeon MP LV L7345 CPU SLA6B G0

19.13.6  Intel Dual-Core Xeon MP E7200 series processor (Tigerton-DC)

Identification


Model name: Dual-Core Xeon MP E7200 series.
Code name: Tigerton-DC.
Supplier: Intel.
Component class: CPU.

Generation


Generation: Core 2.

Compatibility


64 bit technology: EM64T.

Multimedia instruction sets: MMX, SSE, SSE2, SSE3, SSSE3.

Cache


L1 cache: (2x) 32 kbyte instruction cache, 32 kbyte data cache (Harvard architecture).
Two-by-two shared L2 cache: (2x) 4 Mbyte (one per available core).

Architecture


266 MHz QDR Dedicated High Speed Interconnect (DHSI): connecting the CPU socket directly to the chipset on the motherboard (Multi Independent Bus, MIB); main memory talks to the chipset, not directly to the processor chips.

Memory protection: XD bit.

Protected program execution environment: Trusted Execution Technology (TXT; LaGrande Technology, LT).

Virtualization Technology (VT, Vanderpool), with:

  • VT FlexMigration: enabling future processor generations to impersonate a previous generation, allowing virtual machines (vms) to live migrate to another processor generation without disturbing the architectural image that applications are having.

Multi-processing


Quad-core technology: two Dual-Core dies in SMP (Symmetric Multi-Processing) configuration (Dual-Chip Module, DCM).
Only one core per die available; other core disfunctional/disabled.

Symmetric Multi-Processing (SMP): supported through chipset.

Multiplier


Power management


Power management: Enhanced Intel SpeedStep Technology (EIST).

Clock speed


Clock speed Model Multiplier Introduction Order part numbers
266/2400 MHz Intel Duad-Core Xeon MP E7210 CPU 9 September 2007 OEM: LF80564QH0568M
266/2933 MHz Intel Duad-Core Xeon MP E7220 CPU 11 September 2007 OEM: LF80564QH0778M

Physics


Voltage: 1.200-1.325 V.
Power dissipation: 80 W TDP.

Manufacturing process: 65 nm (P1264).

Number of transistors: (2x) 291 million.

Die size: (2x) 143 mm2.

Packaging: Socket 604.

Thermal management


Thermal Monitor: TM1, TM2.

System management


Remote management: Intel Active Management (iAMT2).

CPUID32


Type Family Model Stepping Description
0x0 0x6 0xF 0xB stepping G0

Step level


Text:

Step levels: G0.

S-Spec / Stepping code


Model Code Stepping
Intel Dual-Core Xeon MP E7220 CPU SLA6C G0
Intel Dual-Core Xeon MP E7210 CPU SLA6D G0

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