The ChipList, by Adrian Offerman; The Processor Portal

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AMD Sempron processor (Palermo, revision E3, Socket 939)

Identification


Model name: Sempron.
Code name: Palermo, revision E3.
Family name: Cities.
Supplier: AMD.
Component class: CPU.

Generation


Generation: K8.

Compatibility


No 64 bit technology: AMD64.

Multimedia instruction sets: MMX, Enhanced 3DNow!, SSE, SSE2, SSE3.

Cache


L1 cache: 64 kbyte instruction cache, 64 kbyte data cache (Harvard architecture).
L2 cache: 256 kbyte (other 256 kbyte disfunctional/disabled) or 128 kbyte (other 384 kbyte disfunctional/disabled).

Architecture


128 bit (dual-channel), 200 MHz, DDR memory controller: max. 8 x 512 Mbyte = 4 Gbyte (4 x 1 Gbyte double-sided PC3200 memory module).

800 MHz HyperTransport bus.

Memory protection: NX bit (Enhanced Virus Protection, EVP).

Multiplier


Power management


Power management: Cool'n'Quiet (CnQ).

Clock speed


Clock speed Model Cache Multiplier Introduction Order part numbers
200 MHz / 1.80 GHz AMD Sempron 3000+ CPU 128 kbyte L2 9 October 2005 OEM: SDA3000DIO2BP
200 MHz / 1.80 GHz AMD Sempron 3200+ CPU 256 kbyte L2 9 October 2005 OEM: SDA3200DIO3BP

Physics


Voltage: 1.35-1.40 V.
Power dissipation: 62 W TDP.

Temperature: 0-69 °C.

Manufacturing process: 90 nm.

Number of transistors: 76.0 million.

Die size: 84 mm2.

Packaging: Socket 939.

Step level


Text:

Step levels: E3.

S-Spec / Stepping code


Model Code Stepping
AMD Sempron 3200+ CPU ABBGD E3
AMD Sempron 3000+, 3200+ CPU CBBLE E3
AMD Sempron 3000+ CPU LBBLY E3

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