The ChipList, by Adrian Offerman; The Processor Portal

new
Processor Selector

Platform:
Segment:
Tree: collapse / expand
View: show / edit

bookmark bookmark site
bookmark permalink

AMD Mobile Sempron processor (Keene, revision F2, Low Power)

Identification


Model name: Mobile Sempron.
Code name: Keene, revision F2, Low Power.
Family name: Cities.
Supplier: AMD.
Component class: CPU.

Generation


Generation: K8.

Compatibility


64 bit technology: AMD64.

Multimedia instruction sets: MMX, Enhanced 3DNow!, SSE, SSE2, SSE3.

Cache


L1 cache: 64 kbyte instruction cache, 64 kbyte data cache (Harvard architecture).
L2 cache: 512 kbyte or 256 kbyte (other 256 kbyte disfunctional/disabled).

Architecture


128 bit (dual-channel), 166/333/667 MHz, DDR2-667 memory controller: max. 8 x 512 Mbyte = 4 Gbyte (4 x 1 Gbyte double-sided PC2-5300 memory module).

800 MHz HyperTransport bus.

Memory protection: NX bit (Enhanced Virus Protection, EVP).

No virtualization technology.

Multiplier


Power management


Power management: PowerNow!.

Clock speed


Clock speed Model Cache Multiplier Introduction Order part numbers
200 MHz / 1.60 GHz AMD Mobile Sempron 3200+ CPU 512 kbyte L2 8 May 2006 OEM: SMS3200HAX4CM
200 MHz / 1.80 GHz AMD Mobile Sempron 3400+ CPU 256 kbyte L2 9 May 2006 OEM: SMS3400HAX3CM
200 MHz / 1.80 GHz AMD Mobile Sempron 3500+ CPU 512 kbyte L2 9 May 2006 OEM: SMS3500HAX4CM
200 MHz / 2.00 GHz AMD Mobile Sempron 3600+ CPU 256 kbyte L2 10 October 2006 OEM: SMS3600HAX3CM

Physics


Voltage: 0.950-1.125 V.
Power dissipation: 25 W TDP.

Temperature: max. 95 °C.

Manufacturing process: 90 nm, SoI (Silicon-on-Insulator), 200 mm wafer.

Number of transistors: 103.1 million.

Die size: 81.1 mm2.

Packaging: Socket S1.

Manufactured in: AMD Fab 30/36, Dresden, Germany.

Step level


Text:

Step levels: F2.

S-Spec / Stepping code


Model Code Stepping
AMD Mobile Sempron 3200+, 3600+ CPU LBBVF F2
AMD Mobile Sempron 3400+ CPU LEBAF F2

Page viewed 19997 times since Sun 1 Mar 2009, 0:00.