The ChipList, by Adrian Offerman; The Processor Portal

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7.3  AMD K5 processor

Identification


Model name: K5.
Family name: K86 series.
Supplier: AMD.
Component class: CPU.

Generation


Generation: K5.

Compatibility


Intel Pentium CPU compatible.

Cache


16 kbyte instruction cache with predecode unit, 8 kbyte data cache (Harvard architecture).
Instruction cache: 4-way set-associative, 32 bytes/line, acronym>SI protocol, 2 fetch ports supporting split-line access, 5 predecode bits/byte (10 kbyte), blocking, dual tags, RRR.
Data cache: 4-way set-associative, 32 bytes/line, MESI protocol, dual-ported, blocking, dual tags, write-allocate, 4 banks, RRR.

Architecture


X86 to RISC Operation (ROP) translation.

Superscalar:

  • 5-stage,
  • 3 integer pipelines, 1 FP pipeline.

Dynamic, block oriented, branch prediction with speculative execution.

Physics


Voltage: 3.52 V.

Manufacturing technology: .

  • 3-layer metal, 0.5 micron CMOS (Fab 25, Texas),
  • 0.35 micron CMOS (from Q1 1996).

Packaging: 296 pin SPGA.

Packaging


Packaging:


7.3.1  AMD 5k86 K5 processor

7.3.2  AMD 5k86 SSA/5 processor

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